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System Interface Unit
MOTOROLA
MPC801 USER’S MANUAL
12-23
12
IEXT—Instruction External Transfer Error Acknowledge
This bit is set if the cycle is terminated by an externally generated TEA signal when an
instruction fetch is initiated.
IBM—Instruction Transfer Monitor Timeout
This bit is set if the cycle is terminated by a bus monitor timeout when an instruction fetch is
initiated.
IPB—Instruction Parity Error on Byte
There are four parity error status bits for each 8-bit lane. One of these is set for the byte that
had a parity error when an instruction was fetched. Parity check for a memory region that is
not under memory controller control is enabled by the PNCS bit in SIUMCR.
DEXT—Data External Transfer Error Acknowledge
This bit is set if the cycle is terminated by an externally generated TEA signal when a data
load or store is requested by an internal master.
DBM—Data Transfer Monitor Timeout
This bit is set if the cycle is terminated by a bus monitor timeout when a data load or store
is requested by an internal master.
DPB—Data Parity Error On Byte
There are four parity error status bits for each 8-bit lane. One of these is set for the byte that
had a parity error when a data load was requested by an internal master. Parity check for a
memory region that is not controlled by the memory controller is enabled by the PNCS bit in
the SIUMCR.
12.12.2 System Timer Registers
System timers are powered by keep alive power, which preserves their value when the main
power supply is off. Refer to
Section 5.10.2 The Key Mechanism
for details on the required
actions needed to guarantee data retention.
12.12.2.1 DECREMENTER REGISTER.
The 32-bit PowerPC decrementer (DEC) register
contains values that the down counter uses to cause decrementer interrupts. The
decrementer causes an interrupt whenever Bit 0 changes from logic 0 to logic 1. A read of
this register always returns the current count value from the down counter. The contents of
this register can be read or written to by a
mfspr
or
mtspr
nstruction. This register is not
affected by reset. It uses standby power and continues counting when standby power is
applied.
DEC
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
DEC
BIT
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIELD
DEC