![](http://datasheet.mmic.net.cn/290000/XPC801ZP25_datasheet_16187868/XPC801ZP25_601.png)
Index
Index-10
MPC801
USER’S MANUAL
MOTOROLA
INDEX
development port, 18-42
protection,
18-41
development port,
18-30
DSISR,
6-31
global,
16-13
I
2
C address,
16-31
I
2
C BRG,
16-31
I
2
C command,
16-31
I
2
C event,
16-33
I
2
C mask & interrupt level,
16-34
I
2
C mode,
16-30
I
2
C receive data hold,
16-33
I
2
C transmit data hold,
16-32
instruction,
19-17
internal memory map,
3-1
,
12-20
machine A mode,
15-6
,
15-75
machine B mode,
15-6
,
15-78
memory address,
15-6
,
15-21
,
15-84
memory command,
15-6
,
15-20
memory controller status,
15-6
memory data,
15-6
,
15-20
,
15-84
memory periodic timer prescaler,
15-69
MMU configuration,
11-10
MMU data debug,
11-25
MMU instruction debug,
11-22
MMU tablewalk,
11-14
option,
15-6
,
15-72
,
B-28
periodic interrupt status and control,
12-27
periodic interrupt timer count,
12-28
periodic interrupt timer,
12-29
PLL, low power, and reset control,
5-16
port B data direction,
16-38
port B data,
16-37
port B open-drain,
16-37
port B pin assignment,
16-38
port B,
16-37
real-time clock alarm,
12-27
real-time clock status and control,
12-26
real-time clock,
12-27
receiver,
16-6
reset status,
4-4
serial controller command,
16-15
SIMASK,
12-7
SIPEND,
12-6
SIU interrupt edge level mask,
12-8
SIU module configuration,
12-17
SIVEC,
12-9
software service,
12-22
special purpose, 7-6
,
7-11
added registers,
7-7
unsupported registers,
7-6
SPI command,
16-22
SPI event,
16-25
SPI mask & interrupt level,
16-26
SPI mode,
16-20
SPI receive data hold,
16-24
SPI transmit data hold,
16-23
SRR0,
7-13
SRR1,
7-14
system protection control,
12-21
system timers,
12-23
timebase control and status,
12-25
timebase reference registers,
12-24
timebase,
12-24
transfer error status,
12-22
transmitter,
16-4
registers located outside the core encoding,
6-19
reservation protocol for a multi-level (local)
bus,
13-39
reset
configuration
hard reset,
4-6
soft reset,
4-11
external HRESET,
4-2
internal HRESET,
4-3
reset status register (RSR),
4-4
sequence,
9-12
timing,
20-23
types, 4-1
checkstop reset,
4-3
debug port hard reset,
4-3
debug port soft reset,
4-4
JTAG reset,
4-3
loss of lock,
4-3
power-on reset,
4-2
software watchdog reset,
4-3
reset sequence,
9-12
restrictions, 19-19
watchpoints and breakpoints,
18-12
RETRY,
2-3
,
13-40
RSR,
4-4
,
5-3
RSTCONF,
2-6
RSV,
2-3
,
13-4
,
13-33
RTC,
12-27
RTCAL,
12-27
RTCSC,
12-26
S
sample/preload instruction,
19-18
scan chain interface,
19-19
SCCR,
5-3
,
5-13
SCL,
16-28
SDA,
16-28
SECCOM,
16-15
sequencer unit, 6-4
external interrupt,
6-13
flow control, 6-4
branch folding,
6-5
branch reservation station,
6-5