Development Support
MOTOROLA
MPC801 USER’S MANUAL
18-9
18
In the core, as in other microprocessors, saving and restoring the machine state on the stack
during exception handling is done in the software. When the software is in the middle of
saving or restoring, the MSR
RI
bit is cleared. Exceptions that occur are handled by the core
when the MSR
RI
bit is clear and they result in a nonrestartable machine state. For more
information refer to
Section 6.2.4.1 Restartability After An Interrupt
.
In general, breakpoints are recognized in the core only when the MSR
guarantees machine restartability after a breakpoint. In this working mode, breakpoints are
masked. There are times when it is preferable to enable breakpoints even when the MSR
bit is clear, even though there is the risk of causing a nonrestartable machine state. In
programmable nonmasked mode, an external development system can choose to assert a
nonmaskable external breakpoint. Watchpoints are not masked and are always reported on
the external pins, regardless of the value of the MSR
counting watchpoints, are part of the internal breakpoints logic and are not decremented
when the core is in masked mode and the MSR
watchpoint and breakpoint support of the core.
RI
bit is set, which
RI
RI
bit. The counters, although they are
RI
bit is clear. Figure 18-1 illustrates the
18.2.1 Internal Watchpoints and Breakpoints
This section describes the internal breakpoints and watchpoints support of the core. For
more information on external breakpoints support, refer to
System Interface
. Internal breakpoint and watchpoint support is based on:
Section 18.3 Development
Eight comparators that compare information on instruction and load/store cycles
Two counters
Two AND-OR logic structures
The comparators perform a comparison on the instruction address (I-address), load/store
address (L-address), and load/store data (L-data). The comparators can detect the following
conditions:
Equal to
Not equal to
Greater than
Less than
Greater-than-or-equal-to and less-than-or-equal-to are easily obtained from these four
conditions. Refer to
Section 18.1.1.6 Benefits of Compression
Using the AND-OR logic structures, “in range” and “out of range” detections (on the address
and data comparators) are supported. Using the counters, a breakpoint can be programmed
to be recognized after an event is detected after a predefined number of times.
for more information.