Applications
MOTOROLA
MPC801 USER’S MANUAL
B-45
B
B.6.2 Data Coherency
Changes made in the cache are not made to memory when the cache is in writeback mode.
This creates data coherency problems if another bus master (an SDMA, IDMA, or external
processor) accesses a memory location that has a more recently updated value in the
cache. This can also result in data loss or program execution problems. Thus, writethrough
mode should be used for any memory area that can be accessed by another bus master.
B.6.3 Debugging
The CPU32+ of the MC68360 fetches its instructions from the system bus every time a
particular instruction is executed. By monitoring the external bus, it is easy to determine
which instructions are executing at any given time. Also, areas of memory can be monitored
to determine when reads and writes occur.
When a cache is placed between the core and the system bus, many of the instructions that
are being executed should be out of the sight of the system, thus resulting in better
performance. Ideally, the core fetches instructions from cache rather than external memory,
which makes the fetches invisible, thus complicating the debug process. The same
restriction applies to data reads and, in some cases, writes. This restriction is familiar to
those who have worked with a MC68040 or MC68060. However, the PowerQUICC has
some additional functions in its background debug mode that gives it more debugging
visibility than the MC68040 has.
B.7 MEMORY MANAGEMENT UNIT
Another function of the PowerPC core is that the memory management unit allows the use
of virtual memory and special caching options. The memory management unit on the
PowerQUICC cannot be disabled and using it can be complex.
B.8 REAL-TIME OPERATING SYSTEMS
A real-time operating system (RTOS) can make using the memory management unit on the
PowerQUICC simple. Most commercial RTOS implementations are designed to handle
memory management unit and interrupt schemes, which allow the software designer to
concentrate on more application-specific code than the subtleties of the memory
management unit and interrupts. When porting code from the MC68360 QUICC, keep the
memory management unit, cache, and interrupt handling as special cases.