TABLE OF CONTENTS (Continued)
Paragraph
Number
Page
Number
Title
vi
MPC801
USER’S MANUAL
MOTOROLA
4.2
4.3
4.3.1
4.3.2
Reset Status Register ..........................................................................4-4
How to Configure Reset .......................................................................4-6
Hard Reset .................................................................................4-6
Soft Reset ................................................................................4-11
Section 5
Clocks and Power Control
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.6
5.7
5.8
5.9
5.10
5.10.1
5.10.2
The Clock Module ................................................................................5-3
On-Chip Oscillators and External Clock Input ......................................5-6
The System Phase-Locked Loop .........................................................5-7
Multiplying the Frequency ..........................................................5-7
Eliminating Skew ........................................................................5-7
Operating the PLL Block ............................................................5-8
The Low-Power Divider ........................................................................5-8
Internal Clock Signals ..........................................................................5-9
The General System Clocks ......................................................5-9
The Baud Rate Generator Clock ..............................................5-11
The Synchronization Clocks .....................................................5-11
The Phase-Locked Loop Pins ............................................................5-12
Controlling The System Clock ............................................................5-13
PLL Low-Power and Reset Control Register .....................................5-16
Basic Power Structure ........................................................................5-22
Keep Alive Power ...............................................................................5-23
Configuration ............................................................................5-23
The Key Mechanism ................................................................5-24
Section 6
The PowerPC Core
6.1
6.1.1
6.1.2
6.1.3
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
Features ...............................................................................................6-1
Basic Structure of the Core ........................................................6-2
Instruction Flow Within the Core ................................................6-2
Basic Instruction Pipeline ...........................................................6-4
The Sequencer Unit .............................................................................6-4
Flow Control ...............................................................................6-4
Issuing Instructions ....................................................................6-6
Interrupts ....................................................................................6-6
Precise Exception Model Implementation ..................................6-8
Processing An Interrupt ............................................................6-11
Serialization ..............................................................................6-12
The External Interrupt ..............................................................6-13