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Clocks and Power Control
MOTOROLA
MPC801 USER’S MANUAL
5-17
5
The SPLSS bit is negated by writing a 1 (writing a zero has no effect). The SPLSS bit is not
affected by zero because of a software-initiated loss of lock, which is defined as an
multiplication factor change or entering deep sleep and power-down modes.
0 = SPLL has remained in lock.
1 = SPLL has gone out of lock at least once, but not because of a change with the
PLLEN or MF bits.
TEXPS—Timer Expired Status
This bit is set by a reset. If it is enabled, TEXPS is asserted when the periodic timer expires,
the real-time clock alarm sets, timebase clock alarm is set, or the decrementer interrupt
occurs. The bit stays set until the software clears it. TEXPS is negated by writing a 1 (writing
a zero has no effect). When TEXPS is set, the TEXP external signal is asserted and when
it is reset, the TEXP external signal is negated.
0 = TEXP is negated.
1 = TEXP is asserted.
TMIST—Timers Interrupt Status
This bit is cleared at reset and is set when either the real-time clock, periodic interrupt timer,
timebase, or decrementer interrupt occurs. It is cleared by writing a 1 (writing a zero has no
effect). The system clock frequency remains at a high frequency value defined by the DFNH
bits if the TMIST bit is set. The clock frequency remains high if the CSRC bit in the PLPRCR
is set and there are no conditions for switching to normal low mode.
0 = No timer expiration event is detected.
1 = A timer expiration event is detected.
CSRC—Clock Source
This bit specifies the bit that determines the general system clock—DFNH or DFNL. Setting
this bit switches the general system clock to the DFNL value needed to enter slow-go
low-power mode. Clearing this bit switches the general system clock to the DFNH value.
CSRC is cleared at hard reset.
0 = General system clock is determined by the DFNH value
1 = General system clock is determined by the DFNL value
LPM—Low-Power Modes
These bits are encoded to provide one normal operating mode and four low-power modes.
In normal and doze modes, the system can be in the high state defined by the DFNH bits or
in the low state defined by the DFNL bits. The normal high operating mode is the state out
of reset. This is also the state the bits defer to when the low-power mode exit signal arrives.
In addition, there are four low-power modes—doze, sleep, deep sleep, and power-down.
Table 5-5 provides more details on these bits.