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Clocks and Power Control
MOTOROLA
MPC801 USER’S MANUAL
5-9
5
5.5 INTERNAL CLOCK SIGNALS
The internal logic of the MPC801 uses 9 internal clock signals:
General system clocks—GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50,
and GCLK2_50
Baud rate generator clock—BRGCLK
Synchronization clocks—SYNCCLK and SYNCCLKS
The MPC801 also generates an external clock signal called CLKOUT. The PLL
synchronizes these clock signals to each other.
5.5.1 The General System Clocks
The
general system clocks—GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and
GCLK2_50—are the basic clocks supplied to all modules and submodules on the MPC801.
GCLK1C and GCLK2C are supplied to the PowerPC core, data and instruction caches, and
memory management units and they can be stopped when the core enters the doze
low-power mode. GCLK1 and GCLK2 are supplied to the system interface unit, clock
module, and communication modules.
The external bus clock GCLK2_50 is the same as CLKOUT. The general system clock
defaults to VCO/2 = 40MHz, assuming a 40MHz system frequency. In slow-go mode, the
frequency of the general system clock can be dynamically changed with the SCCR. See
Figure 5-4 for details.
Figure 5-4. General System Clocks Select
The general system clock frequency can be switched between different values. The highest
operational frequency can be achieved when the system clock frequency is determined by
DFNH and DFNH=0. The general system clock can be operated at a low or high frequency.
Low is defined by the DFNL bits of the SCCR and high is defined by the DFNH bits.
Software can change the frequency of the general system clock on-the-fly. The general
system clock can be forced to switch to its low frequency. However, in some applications, a
high frequency is required during certain periods. For example, interrupt routines require a
higher performance than a low frequency operation provides, but they consume less power
than a maximum frequency operation provides.
DFNH DIVIDER
DFNL DIVIDER
VCO/2 (50 MHZ)
DFNH
NORMAL
LOW POWER
GENERAL SYSTEM
CLOCK
DFNL