![](http://datasheet.mmic.net.cn/290000/XPC801ZP25_datasheet_16187868/XPC801ZP25_27.png)
LIST OF TABLES (Continued)
Table
Number
Page
Number
Title
MOTOROLA
MPC801 USER’S MANUAL
xxix
10-1.
10-2.
DC_ADR Bit Functionality for Reading the Cache ..............................10-6
DC_DAT Bit Layout For Reading a Tag ..............................................10-7
11-1.
11-2.
11-3.
11-4.
11-5.
Number of Effective Address Bits Replaced By Real Address Bits .....11-7
Number of Identical Entries Required in the Level One Table ............11-7
Number of Identical Entries Required in the Level Two Table ............11-7
Level One (Segment) Descriptor Format ............................................11-8
Level Two (Page) Descriptor Format ..................................................11-9
12-1.
12-2.
12-3.
Priority of System Interface Unit Interrupt Sources .............................12-5
Multiplexing Control ...........................................................................12-16
Standard Timebase Register Mapping ..............................................12-24
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
MPC801 System Interface Unit Signals ..............................................13-4
Data Bus Requirements For Read Cycles ........................................13-26
Data Bus Contents for Write Cycles ..................................................13-27
BURST/TSIZE Encoding ...................................................................13-33
Definitions of Address Types .............................................................13-34
Termination Signal Protocol ..............................................................13-36
14-1.
PowerPC Little-Endian Effective Address Modification For
Individually Aligned Scalar ..................................................................14-1
Endian Mode Programming For Core Data Structures .......................14-1
Little-Endian Program/Data Path Between the Register and
32-Bit Memory .....................................................................................14-3
Little-Endian Program/Data Path Between the Register and
16-Bit Memory .....................................................................................14-3
Little-Endian Program/Data Path Between the Register and
8-Bit Memory .......................................................................................14-4
14-2.
14-3.
14-4.
14-5.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
Boot Bank Field Values After Reset ..................................................15-16
UPM RAM Word ................................................................................15-25
Byte Select Enable Function .............................................................15-30
Loop Field For UPM Service Requests .............................................15-31
Address Multiplexing .........................................................................15-32
AMA/AMB Definition For DRAM Interfaces .......................................15-33
UPM Start Address Locations ...........................................................15-39
UPM RAM Word Bit Field Example ...................................................15-40