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GT-96100A Advanced Communication Controller
20
Revision 1.0
In HDLC mode, the MPSCs perform all framing operations such as bit stuffing/stripping and flag generation, and
part of the data link operations (e.g. address recognition functions). The MPSCs directly support common HDLC
protocols including those used by ISDN and frame relay. Each MPSC can communicate over dedicated package
pins or through one of four FlexTDM time slot assigners.
1.1.2
FlexTDM Time Slot Assigners
There are four FlexTDM (time slot assigners) in the GT-96100A.
The FlexTDMs support PCM Highway, IOM1, and IOM2 (GCI) formats to allow connections to most WAN
framer and PHY devices. The FlexTDMs are fully programmable and can be configured to support almost any
proprietary TDM bus. They can also be programed to interface voice CODECs and MVIP bus peripherals.
The FlexTDM unit includes two auxiliary channels that can be multiplexed onto the TDM highway with data
from the eight MPSCs. They are optimized for supporting GCI bus Monitor and C/I channels.
1.1.3
10/100 Ethernet Controllers
There are two 10/100-Mbps full duplex Ethernet ports in GT-96100A. Each port is fully compliant with the IEEE
802.3 and 802.3u standards and integrates MAC function and a dual speed MII interface.
The ports’ speed (10 or 100Mb/s) and duplex mode (half or full duplex) is auto-negotiated through the PHY and
does not require user intervention. The ports’ logic also supports 802.3x flow-control mode for full-duplex and
back-pressure mode for half-duplex.
The GT-96100A’s Ethernet ports includes Galileo’s advanced address filtering capability and can be programmed
to accept or reject packets based on MAC addresses, thus providing hardware acceleration to complicated tasks
such as bridging, routing, and firewall. The ports’ can also filter up to 8,000 individual MAC addresses.
1.1.4
SDMA Channels
The GT-96100A offers 20 SDMA channels to support the eight MPSCs and two Fast Ethernet controllers. The
SDMA channels are used to transfer data from the various serial ports to the SDRAM (and vice versa) or over the
PCI. The SDMA channels use linked chain of descriptors and buffers to reduce CPU overhead.
Table 1 summarizes guaranteed throughput of the MPSCs in HDLC mode when the two Fast-Ethernet ports run
at 100Mbit/s full wire speed in full duplex mode.
Table 1:
GT-96100A Serial Performance
No.
Operational Mo de
Aggreg ate Bandwidth
Serial
Ethernet
Total
1
4 ports @55 Mbps simultaneously
440Mbit/s
400Mbit/s
840Mbit/s
2
6 ports @45 Mbps simultaneously
540Mbit/s
400Mbit/s
940Mbit/s
3
All the 8 ports @30 Mbps simultaneously
480Mbit/s
400Mbit/s
880Mbit/s