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GT-96100A Advanced Communication Controller
146
Revision 1.0
The GT-96100A calculates ECC by taking the EVEN parity of ECC check codes of all data bits that are logic
one. For example, if the 64 bit data is 0x45. The binary equivalent is 01000101. From
Table 123, the required
check codes are 00001101 (bit[6]), 01000011 (bit[2]) and 00010011 (bit[0]). Bitwise XOR of this check codes
(even parity) result in ECC value of 01011101.
On a write transaction to a 64-bit wide SDRAM, if ECC is enabled, the GT-96100A calculates the new ECC and
writes it to the ECC bank along with the data that is written to the data bank. Since the ECC calculation is based
on a 64-bit data width, if the write transaction is smaller than 64 bits, the GT-96100A runs a read modify write
sequence.
For a read transaction from a 64-bit wide SDRAM, if ECC is enabled, the GT-96100A reads a 64-bit data and 8-
bit ECC. It calculates ECC based on the 64-bit data and then compares it against the received ECC. The result of
this comparison (bitwise XOR between received ECC and calculated ECC) is called syndrome. If the syndrome
is 00000000, both the received data and ECC are correct. If the syndrome is any other value, it is assumed either
the received data or the received ECC are in error.
If the syndrome contains a single 1, there is a single bit error in the ECC byte. For example, if the received data is
0x45, the calculated ECC is 01011101, as explained before. If the received ECC is 01010101, the resulting syn-
drome is 00001000.
Table 123 shows that this syndrome corresponds to check bit 3. GT-96100A will not report
nor correct this type of error.
If the syndrome contains three or five 1’s, it indicates that there is at least one data bit error. For example, if the
received data is 0x45, the calculated ECC is 01011101, as explained before. If the received ECC is 00011110, the
resulting syndrome is 01000011. This syndrome includes three 1’s and it corresponds to data bit 2 as shown in
Table 123. GT-96100A corrects the data by inverting data bit 2 (the corrected data is 0x41).
If the result syndrome contains two 1’s, it indicates that there is a double-bit error.
If the result syndrome contains four 1’s, it indicates a 4-bit error located in four consecutive bits of a nibble.
If the result syndrome contains three or five 1’s and does not corresponds to any data bit, it indicates a triple-bit
error within a nibble.
These types of errors cannot be corrected. The GT-96100A reports an error but will not change the data.
NOTE: ECC is not supported in bypass mode (data must go through GT-96100A in order to be checked and cor-
rected).
6.1.2
ECC Error Report
If the GT-96100A identifies an ECC data bit error, it sets MemErr bit in Interrupt Cause register (an interrupt is
asserted if not masked).
Additionally, it stores error information in dedicated registers.
The 64-bit data in ECC Upper Data and ECC Lower Data registers.
The ECC byte read from memory in ECC from Memory register.
The calculated ECC byte in ECC Calculated register.
Address bits[31:2] of the erroneous data in ECC Address register. In bits[1:0] it reports whether it was a
single data bit error or multiple data bits error.