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GT-96100A Advanced Communication Controller
280
Revision 1.0
Figure 49: MII Receive Signal Timing
12.4.1.12 10/100 Mbps Full-Duplex Operation
When operating in Full-duplex mode the port can transmit and receive frames simultaneously.
In full-duplex mode, the CrS signal is associated with received frames only and has no effect on transmitted
frames. The Col signal is ignored while in Full-duplex mode. Transmission starts when TxEn goes active. Trans-
mission starts regardless of the state of CrS. Reception starts when the CrS signal is asserted indicating traffic on
the receive port of the PHY.
12.4.1.13 Back Pressure
The port implements a back pressure algorithm, which is only for use when the port is operating in half duplex
mode. It is enabled through Port_Command<FJ> bit.
While in backpressure mode, the port transmits a JAM pattern for a programmable period of time
(JAM_LENGTH). The IPG between two consecutive JAM patterns (or between the last transmit and the first
JAM) is also a programmable value (JAM_IPG). The values are set in Serial_Parameters register.
12.4.1.14 Flow Control
IEEE 802.3x flow control is enabled while in full-duplex mode. Activating this mode is done by setting the
Port_Configuration_Extend<FCTL> bit or by enabling auto-negotiation for Flow-Control, see
Section 12.4.1.4The port supports 802.3x flow-control (PAUSE packets, in the standard term), if it is operating in full-duplex and
if Port_Configuration_Extend<FCTL>=1.
When the port receives a PAUSE packet, it does not transmit a new packet for a period of time specified in this
PAUSE packet.
A received packet is recognized as flow control PAUSE, if it was received without errors and is either of the fol-
lowing:
DA = 01-80-C2-00-00-01 and type=88-08 and MAC_Control_Opcode=01
DA = (The port address) and type=88-08 and MAC_Control_Opcode=01. The 48-bit port address is in
the registers Source_Address_Low, Source_Address_High. This address is also used as source address
for PAUSE packets that the port generates (to DA=01-80-C2-00-00-01)
PAUSE packets are sent by the port when instructed to do so by the CPU. This is done by setting
Port_Command<FJ> bit.
10ns
MIN
RxClk
RxD, RxDV,
RxEr
10ns
MIN
Vih
min
Vil
max
Vih
min
Vil
max