SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
117
PRC1_EXP_INT
The PRC1_EXP_INT bit is set to a logic 1 when a C1 character is received on the receive
protection serial link in its expected position with respect to the RC1FP input. This
interrupt is enabled with the PRC1_EXPE bit in the SBS Interrupt Enable register. This
interrupt bit will be cleared when read.
PRC1_EXTRA_INT
The PRC1_EXTRA_INT bit is set to a logic 1 when a C1 character is received on the
receive protection serial link in an unexpected position with respect to the RC1FP input.
This interrupt is enabled with the PRC1_EXTRAE bit in the SBS Interrupt Enable register.
This interrupt bit will be cleared when read.
PRC1_MISS_INT
The PRC1_MISS_INT bit is set to a logic 1 when a C1 character is not received on the
receive protection serial link in its expected position with respect to the RC1FP input. This
interrupt is enabled with the PRC1_MISSE bit in the SBS Interrupt Enable register. This
interrupt bit will be cleared when read.
ICMP_INT
The ICMP_INT bit is set to a logic 1 when the ICMP input is sampled by the SBS. In
Telecom bus mode, ICMP is sampled during the first C1 position of every frame, as marked
by IC1FP. In SBI mode, ICMP is sampled during the first C1 position of every 4 or 48
frame multi-frame, as marked by IC1FP. This interrupt may be helpful in scheduling
configuration page changes in the IMSU. This interrupt is enabled with the ICMPE bit in
the SBS Interrupt Enable register. This interrupt bit will be cleared when read.
OCMP_INT
The OCMP_INT bit is set to a logic 1 when the OCMP input is sampled by the SBS. In
Telecom bus mode, OCMP is sampled during the first C1 position of every frame, as
marked by RC1FP. In SBI mode, OCMP is sampled during the first C1 position of every 4
or 48 frame multi-frame, as marked by RC1FP. This interrupt may be helpful in scheduling
configuration page changes in the OMSU. This interrupt is enabled with the OCMPE bit in
the SBS Interrupt Enable register. This interrupt bit will be cleared when read.
OCOL_INT[4:1]
If the OCOL_INT[x] bit is a logic 1, an interrupt has been generated from a collision on the
associated outgoing bus. A collision is detected when ODETECT[x] is sampled high during
the same clock cycle that the OACTIVE[x] is set high. These interrupts are enabled with
the OCOLE[4:1] bits in the SBS Interrupt Enable register. These interrupt bits will be
cleared when read.