SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
326
These registers should not be used in SBI mode. In TelecomBus mode, the registers act as an
OR function with existing J1 indicators, and should not be used with STS/AUs where J1 is
floating. When J1 is fixed to 0 or 522, the incoming J1 from the serial link will still propagate
through the device, and setting the appropriate J1 indicator will have no additional effect;
however, V1 insertion may be used in this case to mark the multiframe.
13.13 “C1” Synchronization
Any NSE/SBS fabric can be viewed as a collection of five “columns” of devices: column 0
consists of the ingress flow from the load devices (e.g., some SBI device); column 1 consists of
the ingress flow through the SBS devices; column 2 consists of the NSE-20G device; column 3
consists of the egress flow through the SBS devices; and column 4 consists of the egress flow
through the load devices (e.g. some SBI device). Note that the devices in columns 0 and 4 are
SBI bus devices while columns 1 and 3 are SBS or SBSLITE devices. The dual column
references refer to their two separate simplex flows. Path-aligned STS-12/STM-4 frames are
pipelined through this structure in a regular fashion, under control of a single clock source and
frame pulse. There are latencies between these columns, and these latencies may vary from
path to path. The following design is used to accommodate these latencies.
A timing pulse for SBI frames (2kHz, 500 s) is generated and fed to each device in the fabric.
Each chip has a
FrameDelay
register (RC1DLY) which contains the count of 77.76 MHz clock
ticks that device should delay from the reference timing pulse before expecting the C1
characters of the ingress STS-12/STM-4 frames to have arrived. The base timing pulse is called
t
. The delays from
t
based on the settings of the RC1DLY registers in the successive columns of
the devices are called
t0, … t4
. The first signal, t
1
(equal to t
0
), determines the start of an STS-
12/STM-4 frame; this signal is used to instruct the ingress load devices (column 0) to start
emitting an STS-12/STM-4 frame (with its special “C1” control character) at that time. ti is
determined by the customer, based on device and wiring delays to be approximately the earliest
time that all “C1” characters will have arrived in the ingress FIFOs of the ti column of devices.
ti is selected to provide assurance that all “C1” characters have arrived at the i
th
column. The i
th
column of devices use the ti signal to synchronize emission of the STS-12/STM-4 frames. The
ingress FIFOs permit a variable latency in C1 arrival of up to 24 clock cycles.
Note: the SBS device, being a memory switch adds a latency of one complete frame plus a few
clock ticks to the data in DS0 switching mode. In column switching mode, the latency is one
row plus a few clock ticks.