SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
15
Figure 39 Receive SBI336 Functional Timing.........................................................................346
Figure 40 Receive LVDS Link Timing .....................................................................................347
Figure 41 Outgoing Synchronization Timing (77.76MHz Telecom Bus).................................347
Figure 42 Outgoing 77.76MHz TelecomBus Functional Timing..............................................348
Figure 43 Outgoing 19.44MHz TelecomBus Functional Timing..............................................349
Figure 44 Outgoing SBI336 Functional Timing .......................................................................349
Figure 45 Outgoing SBI Bus Functional Timing......................................................................350
Figure 46 Analog Power Filter Circuit......................................................................................353
Figure 47 Microprocessor Interface Read Timing...................................................................356
Figure 48 Microprocessor Interface Write Timing ...................................................................358
Figure 49 SBS Incoming Timing..............................................................................................360
Figure 50 SBS Receive Timing...............................................................................................362
Figure 51 SBS Outgoing Timing..............................................................................................364
Figure 52 SBS Outgoing Bus Collision Avoidance Timing......................................................365
Figure 53 SBS Transmit Timing..............................................................................................366
Figure 54 SYSCLK / REFCLK Skew Requirement.................................................................367
Figure 55 SYSCLK / SREFCLK Timing – 19.44MHz mode....................................................367
Figure 56 RSTB Timing...........................................................................................................368
Figure 57 JTAG Port Interface Timing.....................................................................................369
Figure 58 352 Pin UBGA 27x27mm Body...............................................................................372