SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
27
7
Description
The PM8610 SBI336 Bus Serializer, SBS, is a monolithic integrated circuit that implements
conversion between byte-serial 19.44Mhz SBI bus or 77.76MHz SBI336 bus and redundant
777.6Mbps bit-serial 8B/10B-base SBI336S bus. In telecom bus mode the SBS implements
conversion between any 19.44MHz Telecom bus or 77.76MHz Telecom bus format and
redundant 777.6Mbps bit-serial 8B/10B-base serial telecom bus format. In line with the bus
conversion is a DS0 granular switch allowing any input DS0 to be output on any output DS0.
The redundant 777.6 Mbps serial interfaces can be disabled and a byte-wide SBI336 bus can be
enabled in its place with all the DS0 level switching capabilities.
The SBS can be used to connect and switch high-density T1/E1 framer devices supporting an
SBI bus with link layer devices supporting an SBI bus over a serial backplane. Putting the
Narrowband Switch Element, NSE, between the framer and link layer devices allows
construction of up to 20Gb/s NxDS0 switches.
In the ingress direction, the SBS connects an incoming SBI stream to a pair of redundant serial
SBI336S LVDS links through a DS0 memory switch. The incoming SBI bus can be either a
single 77.76MHz SBI bus (SBI336) or four 19.44MHz SBI buses (SBI). In telecom bus mode
an incoming 77.76MHz telecom bus or four 19.44MHz telecom buses that have the J1 path
fixed and all high order pointer justifications converted to tributary pointer justifications can be
switched through a VT/TU granular switch to a pair of redundant serial LVDS telecom bus
format links. The incoming data is encoded into an extended set of 8B/10B characters and
transferred onto two redundant 777.6 Mbps serial LVDS links. SBI or telecom bus frame
boundaries, pointer justification events and master timing controls are marked by 8B/10B
control characters. Incoming SPEs may be optionally overwritten with the locally generated X
23
+ X
18
+ 1 PRBS pattern for diagnosis of downstream equipment. The PRBS processor is
configurable to handle any combination of SPEs and can be inserted independently into either
of the redundant LVDS links. A DS0 memory switch provides arbitrary mapping of streams on
the incoming SBI bus stream(s) to the working and protect LVDS links at DS0 granularity. In
telecom bus mode a VT/TU memory switch provides arbitrary mapping of tributaries on the
incoming telecom bus stream(s) to the working and protect LVDS links. Multi-cast is supported.
In the egress direction, the SBS connects two independent 777.6 Mbps serial LVDS links to an
outgoing SBI Bus. Each link contains a constituent SBI336S stream. Bytes on the links are
carried as 8B/10B characters. The SBS decodes the characters into data and control signals for
a single 77.76MHz SBI336 bus or four 19.44MHz SBI buses. Alternatively the SBS decodes
two independent 777.6 Mbps telecom bus formatted serial LVDS links characters into a single
77.76MHz or quad 19.44MHz telecom buses. A pseudo-random bit sequence (PRBS) processor
is provided to monitor the decoded payload for the X
23
+ X
18
+ 1 pattern in each SPE. The
PRBS processor is configurable to handle any combination of SPEs in the serial LVDS link.
Data on the outgoing SBI bus stream(s) may be sourced from either of the LVDS links.
An In-band signaling link over the serial LVDS links allows this device to be controlled by a
companion-switching device, the Narrowband Switching Element, NSE20G. This link can be
used as communication link between a central processor and the local microprocessor.