SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
49
Pin Name
Type
Pin
No.
Function
Changes to the connection memory page selection are
synchronized to the frame boundary (A1 byte position)
of the next frame.
OCMP is sampled on the rising edge of SYSCLK.
RWSEL
Input
AD23
Receive Working Serial Data Select.
The receive
working serial data select signal, RWSEL, selects
between sourcing outgoing data, ODATA[4:1][7:0], from
the receive working serial data link, RPWRK/RNWRK,
or the receive protect serial data link,
RPPROT/RNPROT. When RWSEL is set high, the
working serial bus is selected. When RWSEL is set
low, the protect serial bus is selected. RWSEL is
sampled at the C1 byte location as defined by the
receive serial interface frame pulse signal, RC1FP.
Changes to the selection of the working and protect
serial streams are synchronized to the SBI frame
boundary of the next frame.
RWSEL is sampled on the rising edge of SYSCLK.
IUSER2
Input
AC15
Input In-band Link User Signal.
The input in-band link
user signal, IUSER2, provides external control over one
of the bits in the in-band link. The USER[2] bit in the
header of the in-band signaling channel of both the
working and protection serial links will reflect the state
of this input.
IUSER2 an asynchronous signal and is internally
synchronized to SYSCLK.
OUSER2
Output
AA1
Output In-Band Link User Signal.
The output in-band
link user signal, OUSER2, reflects the state of the
USER[2] bit in the header of the in-band signaling
channel of either the working or the protection serial
link, whichever is active.
OUSER2 is an asynchronous output.
RSTB
Input
AC22
Reset Enable Bar.
The active low reset signal, RSTB,
provides an asynchronous SBS reset. RSTB is a
Schmitt triggered input with an integral pull-up resistor.
When performing a reset of the SBS, this pin should be
held low for a minimum of 1ms to properly reset the
CSU. Alternatively, the ARESET bit in register 000H
must be set for a minimum of 1ms after the SBS is reset
by RSTB.
JTAG Interface (5 Signals)
TCK
Input
P2
Test Clock.
The JTAG test clock signal, TCK, provides
timing for test operations that are carried out using the
IEEE P1149.1 test access port.
TMS
Input
P3
Test Mode Select.
The JTAG test mode select signal,
TMS, controls the test operations that are carried out
using the IEEE P1149.1 test access port. TMS is
sampled on the rising edge of TCK. TMS has an
integral pull-up resistor.
TDI
Input
R1
Test Data Input.
The JTAG test data input signal, TDI,
carries test data into the SBS via the IEEE P1149.1 test