SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
323
Byte errors are accumulated only when the monitor is in synchronized state. To enter the
synchronize state, the monitor must have synchronized to the incoming PRBS stream and
received 4 consecutive bytes without errors. Once synchronized, the monitor falls out of
synchronization when forced to by programming the RESYNC register bit high, or once it
detects 3 consecutive PRBS byte errors. When out of synchronization, detected errors are not
accumulated.
13.11 Using the In-Band Link Controller (WILC and PILC)
The In-Band Link Controllers provides a mechanism for communication between devices over
the serial interface. The ILC inserts and retrieves messages from the transport overhead of the
SBI336 or Telecom Bus frame. The messages are 36 bytes each and 4 messages are transmitter
each frame. These messages are inserted into the Data Communication Channel (DCC) bytes,
in rows 3,6,7 and 8. Each message contains 2 header bytes, 32 bytes containing the free format
information, and 2 bytes for a CRC-16. There is an independent in-band link controller for
working and the protection links (WILC for the working link and PILC for the protection link).
If no information bytes are available to transmit, the ILC will continue to send messages but
will insert all zeros into the information bytes and will set the VALID bit in the header to zero.
The header and CRC bytes will be transmitted normally. When the receive link recognizes that
the VALID bit is a zero, it will not write the all zero message into the receive FIFO.
13.11.1
Transmitting Messages
When writing to the transmit FIFO in the WILC or PILC, the following procedure should be
followed:
Write a logic 1 to the TX_XFER_SYNC bit of the Transmit Status and FIFO Synch Register
(095H or 0A5H). This will ensure the subsequent writes to the FIFO start at the beginning of a
message.
Write to the Transmit Data High Register (090H or 0A0H).
Write to the Transmit Data Low Register (091H or 0A1H). Writing to this register will initiate a
transfer of the Transmit Data High Register and Transmit Data Low Register into the transmit
FIFO.
Read the TX_FI_BUSY bit in the Transmit Status and FIFO Synch Register (095H or 0A5H) or
wait a minimum of 3 SYSCLK cycles. If TX_FI_BUSY is a logic 0, continue to step 5. If it is
a logic 1, continue polling the TX_FI_BUSY bit.
Loop back to Step 2 until the entire message has been written in to the FIFO.
When transmitting multiple 32 byte messages, the TX_XFER_SYNC bit does not have to be
written to between each message.
When transmitting a message shorter than 32 bytes, the TX_XFER_SYNC bit should be set
after writing the last byte of the message into the FIFO. This will allow the short message to be
transmitted and move the FIFO to the next 32 byte partition.