SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
319
The selection of the termination mode is contained in registers 0B2H and 0B3H for the TW8E,
and in registers 0BAH and 0BBH for the TP8E.
13.8 Interpreting the Status of the Receive Decoders (RW8D and
RP8D)
The receive decoded blocks (RW8D and RP8D) produce interrupts based on four receiver
conditions or events: OCA (Out of Character Alignment), OFA (Out of Frame Alignment), FUO
(FIFO Underrun/Overrun) and LCV (Line Code Violation). Understanding the relationship
between these conditions can help to diagnose device status. These conditions have the
following interrelationships:
OCA implies OFA until character alignment is re-achieved. OCA will most likely cause some
LCVs but not necessarily a continual stream. Since character boundaries are not know, framing
and disparity are meaningless.
OFA, by itself, does not cause any of the other conditions.
FUO may produce zero, one or many OCVs, depending on how the FIFO underrun/overrun
occurs.
Persistent LCVs (five or more in any sequence of 15 characters) cause OCA.
13.9 Using the Memory Switch Units (IMSU and OMSU)
The Memory Switch Unit (MSU) blocks in the SBS (IMSU and OMSU) can be used to
rearrange the position of the bytes (or columns) within the SBI336 or Telecom Bus frame. Each
block buffers an entire frame (9720 bytes) or row (1080 columns) and rearranges them before
outputting them.
13.9.1
Selection Between the Two Connection Memory Pages
The selection of which input byte (or column) is to be output at each output byte (or column)
location is controlled by the settings in the connect memory pages. There are two connection
memory pages, one of which is used to control the switching function while the other may be
modified with new connections through the microprocessor interface.
The two pages can be swapped by changing the CMP value. There are three possible sources
for the CMP value. They are the ICMP/OCMP input pins, the ICMP_VAL/OCMP_VAL bits in
the SBS Master Configuration Register (001H), and the PAGE[1:0] bits from the ILC block on
the active receive link. The selection of the source of CMP is controlled by the setting of the
ICMP_SRC[1:0]/OCMP_SRC[1:0] bits in the SBS Master Configuration Register (001H).
13.9.2
Procedure for Writing to the Connection Memory Page
When writing to a location in the connection memory page in the IMSU or OMSU, the
following procedure should be followed:
Write the desired configuration into the Indirect Time Switch Data Register.