SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
316
13.4 Interrupt Service Routing
The SBS will assert the INTB output to a logic 0 when a condition that is configured to produce
an interrupt occurs. To find which condition caused this interrupt to occur, the procedure
outlined below should be followed:
Read the SBS Master Interrupt Source Register (010H) to find the functional block which
caused the interrupt.
Find the register address of the corresponding block that caused the interrupt and read its
Interrupt Status registers. The interrupt bits in the functional block and the interrupt source
identification bits from step 1 are cleared once these register(s) have been read and the
interrupt(s) identified.
Service the interrupt(s).
If the INTB pin is still logic 0, then there are still interrupts to be serviced and steps 1 to 3 need
to be repeated. Otherwise, all interrupts have been serviced. Wait for the next assertion of
INTB.
Note that all interrupts in the SBS may be disabled by setting the INTE bit of the SBS Master
Interrupt Enable Register (016H) to a logic 0. Interrupts may also be disabled on a block by
block basis by setting the appropriate block enable bits in this register to a logic 0.
13.5 Accessing Indirect Registers
Indirect registers are used to conserve address space in the SBS.
13.5.1
Accessing Indirect Registers in the ICASM, OCASM, ISTT, OSTT and OSTA
When writing to an indirect register in the ICASM, OCASM, ISTT, OSTT or OSTA, the
following procedure should be followed:
Read the BUSY bit in the Indirect Access Control Register. If it is a logic 0, continue to step 2.
If it is a logic 1, continue polling the BUSY bit.
Write the desired configuration for the tributary into the Indirect Access Data Register.
Write the desired tributary number into the Indirect Access Address Register.
Write to the Indirect Access Control Register with RWB set to logic 0.
Read the BUSY bit. Once it is a logic 0, the indirect write has been completed.
When reading an indirect register from the ICASM, OCASM, ISTT, OSTT or OSTA, the
following procedure should be followed:
Read the BUSY bit in the Indirect Access Control Register. If it is a logic 0, continue to step 2.
If it is a logic 1, continue polling the BUSY bit.