SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
85
Aux[7:0]
Table 23 In-band Message Header Fields
Field Name
Received by SBS
Transmitted by SBS
Valid
Message slot contains a valid
message(1) or is empty(0). If empty
this message will not be put into Rx
Message FIFO (other header
information processed as usual)
Message slot contains a valid
message(1) or is empty(0). The
header and CRC bytes are
transmitted regardless of the state of
this bit.
Link[1:0]#
Each bit indicates which Link to use,
working(0) or Protect(1). Other
algorithms are possible in indicate
Working or Protect over these 2 bits.
Each bit shows current Link in use,
working(0) or Protect(1). Other
algorithms are possible in indicate
Working or Protect over these 2 bits.
These bits are transmitted
immediately.
Page[1:0]#
Each bit indicates which configuration
page to use, page (1) or page (0) for
the corresponding MSU. Page[1]
controls the IMSU configuration page
and Page[0] controls the OMSU
configuration page.
Each bit shows current control page in
use, page (1) or page (0) for the
corresponding MSU. Page[1]
indicates the IMSU configuration page
and Page[0] indicates the OMSU
configuration page
Only transmitted from the beginning of
the first message of the frame
User[2:0]#
User defined bits which may be read
through the microprocessor interface.
User[2] is also output from the SBS on
the OUSER2 pin.
User defined bits. User[2] is sourced
from the IUSER2 input to the SBS.
User[1:0] are sourced from an internal
register.
Transmitted immediately.
Aux[7:0]#
User defined auxiliary register
indication.
User defined auxiliary register
indication.
Transmitted immediately.
#Change in these bits(received side) will not be processed if the received message CRC-16
indicates an error.
Interrupts can be generated when CRC errors are detected or the USER or LINK bits change
state. There is no inherent flow control provided by the In-Band Link Controller. The attached
microprocessor is able to provide flow control via interrupts when the in-band message FIFO
overflows and via the USER bits in the header.
As each message arrives, the CRC-16 and valid bit is checked; if the valid bit is not set the
message is discarded, if it fails the CRC check it is flagged as being in error and an interrupt is
generated if enabled. If the CRC-16 is OK, regardless of the valid bit, the Page Link, User and
Aux bits are passed on immediately. If the FIFO erroneously overflows, an interrupt is
generated.