SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
46
Pin Name
Type
Pin
No.
Function
during any available information byte to indicate to the
slave timed SBI336 device that the timing master
device is able to accept another byte of data. For every
byte that this signal is asserted high the slave device is
expected to send a valid byte of data.
All timing adjustments from the slave timed device in
response to the justification request must still set the
payload and payload indicators appropriately for timing
adjustments.
TJUST_REQ is updated on the rising edge of SYSCLK.
Microprocessor Interface (30 Signals)
CSB
Input
AB25
Chip Select Bar.
The active low chip select signal
(CSB) controls microprocessor access to registers in
the SBS device. CSB is set low during SBS
Microprocessor Interface Port register accesses. CSB
is set high to disable microprocessor accesses.
If CSB is not required (i.e. register accesses controlled
using RDB and WRB signals only), CSB should be
connected to an inverted version of the RSTB input.
RDB
Input
AA25
Read Enable Bar.
The active low read enable bar
signal (RDB) controls microprocessor read accesses to
registers in the SBS device. RDB is set low and CSB is
also set low during SBS Microprocessor Interface Port
register read accesses. The SBS drives the D[15:0]
bus with the contents of the addressed register while
RDB and CSB are low.
WRB
Input
AA26
Write Enable Bar.
The active low write enable bar
signal (WRB) controls microprocessor write accesses to
registers in the SBS device. WRB is set low and CSB
is also set low during SBS Microprocessor Interface
Port register write accesses. The contents of D[15:0]
are clocked into the addressed register on the rising
edge of WRB while CSB is low.
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
I/O
AE20
AD19
AF16
AD15
AE15
AF15
AD14
AC11
AD10
AF6
AC8
AD7
AF4
AC6
AD5
AE4
Microprocessor Data Bus.
The bi-directional data
bus, D[15:0] is used during SBS Microprocessor
Interface Port register reads and write accesses. D[15]
is the most significant bit of the data words and D[0] is
the least significant bit.
A[8]/TRS
A[7]
A[6]
A[5]
A[4]
Input
AF3
AC5
AD4
AD1
AC2
Microprocessor Address Bus.
The microprocessor
address bus (A[8:0]) selects specific Microprocessor
Interface Port registers during SBS register accesses.
A[8] is also the Test Register Select (TRS) address pin