SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
325
AUX[7:0]:
These bits reflect the state of the TX_AUX[7:0] bits in the Transmit Control
Register (093H or 0A3H).
13.11.4
Receive Message Header Bytes
LINK[1:0]:
The LINK[1:0] bits from the latest received message are reflected in the
RX_LINK[1:0] bits of the Receive Status and FIFO Synch Register (09DH or 0ADH). These
bits are only update if the receive message contains a correct CRC value. If the CRC is in error,
these bits will keep their previous value. A change in state of either of these bits can be
configured to cause an interrupt by setting the RX_LINK_CHGE bit in the Interrupt Enable and
Control Register (09DH or 0ADH).
PAGE[1:0]:
The PAGE[1:0] bits from the latest received message are reflected in the
OPAGE[1:0] bits of the Receive Status and FIFO Synch Register (09DH or 0ADH). The
PAGE[1:0] bits on the active link (as selected by RWSEL) may be used to control the
connection memory pages of the MSU blocks. PAGE[1] will control the CMP value for the
IMSU when the ICMP_SRC[1:0] bits in register 001H are set to “10”. PAGE[0] will control
the CMP value for the OMSU when the OCMP_SRC[1:0] bits in register 001H are set to “10”.
These bits are only update if the receive message contains a correct CRC value. If the CRC is
in error, these bits will keep their previous value. A change in state in either of these bits can be
configured to cause an interrupt by setting the OPAGE_CHGE[1:0] bits in the Interrupt Enable
and Control Register (09DH or 0ADH).
USER[2:0]:
The USER[2:0] bits from the latest received message are reflected in the
OUSER[2:0] bits of the Receive Status and FIFO Synch Register (09DH or 0ADH). The
USER[2] from the active link (as selected by RWSEL) will also be output on the OUSER2
output of the SBS. These bits are only update if the receive message contains a correct CRC
value. If the CRC is in error, these bits will keep their previous value.
AUX[7:0]:
The AUX[7:0] bits from the latest received message are reflected in the
RX_AUX[7:0] bits of the Receive Auxiliary Register (09AH or 0AAH). These bits are only
update if the receive message contains a correct CRC value. If the CRC is in error, these bits
will keep their previous value.
13.11.5
Disabling the ILC
The functions of the WILC and PILC blocks may be disabled. When disabled, no messages are
inserted or retrieved. All data passes through the ILC unmodified.
The TX_BYPASS bit in the Transmit Control Register (093H or 0A3H) will disable the transmit
half of the ILC. The RX_BYPASS bit in the Receive FIFO Control Register (099H or 0A9H)
will disable the receive half of the ILC.
13.12 Using J1 and V1 insertion registers
Registers 061H and 062H allow for the insertion of J1 and V1 indicators on the OC1FP signal.
By using these registers, it is possible to insert J1 and V1 indicators at STS/AU granularity. The
OLOCK0 bit in register 060H controls the position of the J1 indicators, which may either follow
C1 (Z0) or H3. On the multiframe, V1 indicators always follow the J1 indicator.