SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
65
Table 12 DS3 Framing Format
SPE
COL #
SBI COL#
1,4,7,10
DS3
1
16
DS3
2-56
DS3
57
184
DS3
58-84
DS3
Col 85
268
ROW
13
1
Unused
H1
V5
DS3
DS3
DS3
DS3
2
Unused
H2
DS3
DS3
DS3
DS3
DS3
3
Unused
H3
DS3
DS3
DS3
DS3
DS3
4
Unused
Linkrate
DS3
DS3
DS3
DS3
DS3
5
Unused
Unused
DS3
DS3
DS3
DS3
DS3
6
Unused
Unused
DS3
DS3
DS3
DS3
DS3
7
Unused
Unused
DS3
DS3
DS3
DS3
DS3
8
Unused
Unused
DS3
DS3
V5
DS3
DS3
9
Unused
Unused
DS3
DS3
DS3
DS3
DS3
Because the DS3 tributary rate is less than the rate of the gray region, padding octets are
interleaved with the DS3 tributary to make up the difference in rate. Interleaved with every DS3
multi-frame are 35 stuff octets, one of which is the V5 octet. These 35 stuff octets are spread
evenly across seven DS3 subframes. Each DS3 subframe is eight blocks of 85 bits. The 85 bits
making up a DS3 block are padded out to be 11 octets. Table 13 shows the DS3 block 11 octet
format where R indicates a stuff bit, F indicates a DS3 framing bit and I indicates DS3
information bits. Table 14 shows the DS3 multi-frame format that is packed into the gray region
of Table 12. In this table V5 indicates the V5 octet which is also a stuff octet, R indicates a stuff
octet and B indicates the 11 octet DS3 block. Each row in Table 14 is a DS3 multi-frame. The
DS3 multi-frame stuffing format is identical for 5 multi-frames and then an extra stuff octet
after the V5 octet is added every sixth frame.
Table 13 DS3 Block Format
Octet #
Data
1
RRRFIIII
2
8*I
3
8*I
4
8*I
5
8*I
6
8*I
7
8*I
8
8*I
9
8*I
10
8*I
11
8*I
Table 14 DS3 Multi-frame Stuffing Format
V5
4*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
V5
4*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
V5
4*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
V5
4*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
V5
4*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
V5
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
5*R
8*B
DS3 asynchronous timing is compensated via the H3 octet as described in section 10.1.2. DS3
link rate adjustments are optionally passed across the SBI via the Linkrate octet as described in
section 10.1.3. DS3 alarm conditions are optionally passed across the SBI bus via the Linkrate
octet as described in section 10.1.3 and 10.1.4.