SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
95
COLUMN_MODE
The COLUMN_MODE bit selects between column switching and DS0 switching. When
COLUMN_MODE is set to a logic 1, column switching is enabled and the SBS is
configured to switch columns within the SBI336 or Telecom bus. When COLUMN_MODE
is set to a logic 0, DS0 switching is enabled and the SBS is configured to switch DS0’s
within the SBI336 bus. DS0 switching is not permitted in Telecom Bus mode.
PHY_SBI
The PHY_SBI bit configures the direction of the JUST_REQ[4:1] input/output signals on
the incoming and outgoing buses. When PHY_SBI is set to a logic 1, the SBS is configured
to be connected to a PHY device and the JUST_REQ[4:1] signal is an input. When
PHY_SBI is set to a logic 0, the SBS is configured to be connected to a Link layer device
and the JUST_REQ[4:1] signal is an output.
MF_48
The MF_48 bit selects between 4 frame multi-frame mode or 48 frame multi-frame mode
on the SBI336 bus. When MF_48 is a logic 1, 48 frame mode is selected. IC1FP is
expected once every 48 frames and OC1FP is output every 48 frames, indicating CAS
signaling multi-frame alignment. When MF_48 is a logic 0, 4 frame mode is selected.
IC1FP is expected once every 4 frames and OC1FP is output every 4 frames. This bit has
no effect when in Telecom bus mode (TELECOM_BUS = ‘b1) or when in column
switching mode (COLUMN_MODE = ‘b1).
TELECOM_BUS
The TELECOM_BUS bit selects between Telecom bus and SBI bus modes on the incoming
and outgoing buses. When TELECOM_BUS is set to a logic 1, Telecom bus mode is
selected and all frame pulses must mark C1J1V1 positions. When TELECOM_BUS is set
to a logic 0, SBI bus mode is selected and the all frame pulses only mark the C1 position.
19M_BUSB
The 19M_BUSB bit selects between 19MHz and 77MHz mode on the incoming and
outgoing buses. When 19M_BUSB is set to a logic 0, 19MHz mode is selected and 4
separate 19MHz buses are used. When 19M_BUSB is set to a logic 1, 77MHz mode is
selected and a single 77MHz bus is used.
Note:
Whenever this bit is changed from a logic 0 to a logic 1, the REFDLL must be reset
by writing to register 0E2H.