SBI Bus Serializer ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2000168, Issue 5
4
Revision History
Issue No. Issue Date
Details of Change
5
June, 2002
Created Issue 5 of the data sheet.
General pre-production review and update.
Updated SBI336 and SBI structure tables and cleaned up framing format
tables.
Added AMODE requirement in TelecomBus mode.
Added a note pertaining to analog power filtering requirements, and
corrected these requirements.
Removed OPA section and replaced it with a reference to the application
notes.
Documented RX_INV bit in registers 0C0 and 0C8.
Updated power requirements.
Added more information on device latency.
Added timing relationship between IC1FP and RC1FP for the DS0
loopbacks in register 02B and 04B.
Updated thermal information based on new simulation data.
Updated Microprocessor Timing diagram to reflect correct data bus width.
Added 4xOC-3/4xSTM-1 Voice Processing Card diagram.
4
February, 2002
Created Issue 4 of the data sheet to reflect the following changes:
Updated block diagram to reflect the new order of blocks. ISTT is now
located in between the ISTA and the
ICASE and OSTT is now located between the OCASM and OSTA
Explained the differences between the HPT, MST and the LPT modes.
Pin description of OACTIVE changed to indicate it should be ignored in
77MHz mode.
Pin description of ODETECT changed to indicate that it must be held low
in Telecom bus mode.
Updated pin description for RSTB to indicate that is must be held low for a
minimum of 1ms to reset the CSU.
Updated pin description for RES and RESK. Separated CSU_AVDL pins
from AVDL pins.
Added analog filtering requirements.
CSU description updated to state that it must be reset for a minimum of
1ms.
Updated ARESET bit description in register 000h.
Changed SBI_19M to SBI_19MB in register 001h to reflect the actual
polarity of the bit.
Changed the meaning of SPE_TYP bits in register 005h and 006h.
Added C1 interrupts to register 011h and added interrupt enables to
register 012h.
Fixed bit description in register 016h. Added SPE_TYP registers 018h,
019h, 01Ah and 01Bh.
Added restriction to registerS 03Ah and 042h stating that they must not be
set in parallel mode.
Added OMUS overwrite function to register 04Bh.
Fixed description of ERR_CNT in register 071h and 081h (IADDR=4h).
Updated description of MONx_SYNCV in register 07Bh and 08Bh.
Updated description of DLCV in register 0B0H and 0B8H.
Updated description of RX_XFER_SYNC in register 09Bh and 0ABh.
Updated description of DLCV in register 0B0H and 0B8H. Added REFDLL
and SYSDLL reset registers 0E2h and 0EAh.
Updated JTAG ID.
Updated Transmit and Receive LVDS timing diagrams.
Updated Operation section, Absolute Maximum Ratings and D.C.
Characteristics.
Added Serial Interface Timing, RSTB Timing and SYSCLK / SREFCLK