參數(shù)資料
型號(hào)： KM416RD4C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司）
文件頁(yè)數(shù)： 26/59頁(yè)
文件大?。?/td> 4654K
代理商： KM416RD4C
Page 27
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
Control Register Transactions
The RDRAM has two CMOS input pins SCK and CMD and
two CMOS input/output pins SIO0 and SIO1. These provide
serial access to a set of control registers in the RDRAM.
These control registers provide configuration information to
the controller during the initialization process. They also
allow an application to select the appropriate operating mode
of the RDRAM.
SCK (serial clock) and CMD (command) are driven by the
controller to all RDRAMs in parallel. SIO0 and SIO1 are
connected (in a daisy chain fashion) from one RDRAM to
the next. In normal operation, the data on SIO0 is repeated
on SIO1, which connects to SIO0 of the next RDRAM (the
data is repeated from SIO1 to SIO0 for a read data packet).
The controller connects to SIO0 of the first RDRAM.
Write and read transactions are each composed of four
packets, as shown in Figure Figure and Figure Figure. Each
packet consists of 16 bits, as summarized in Table 14 and
Table 15. The packet bits are sampled on the falling edge of
SCK. A transaction begins with a SRQ (Serial Request)
packet. This packet is framed with a 11110000 pattern on the
CMD input (note that the CMD bits are sampled on both the
falling edge and the rising edge of SCK). The SRQ packet
contains the SOP3..SOP0 (Serial Opcode) field, which
selects the transaction type. The SDEV4..SDEV0 (Serial
Device address) selects one of the 32 RDRAMs. If SBC
(Serial Broadcast) is set, then all RDRAMs are selected. The
SA (Serial Address) packet contains a 12 bit address for
selecting a control register.
A write transaction has a SD (Serial Data) packet next. This
contains 16 bits of data that is written into the selected
control register. A SINT (Serial Interval) packet is last,
providing some delay for any side-effects to take place. A
read transaction has a SINT packet, then a SD packet. This
provides delay for the selected RDRAM to access the
control register. The SD read data packet travels in the oppo-
site direction (towards the controller) from the other packet
types. The SCK cycle time will accomodate the total delay.
Figure 23 : Serial Write (SWR) Transaction to Control Register
SRQ - SWR command
1111
00000000...00000000
SRQ - SWR command
0000
SA
SA
SD
SD
SINT
SINT
00000000...00000000
00000000...00000000
00000000...00000000
SCK
CMD
SIO0
SIO1
T
4
T
36
T
20
T
52
T
68
Each packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
1111
next transaction
Figure 24 : Serial Read (SRD) Transaction Control Register
SRQ - SRD command
1111
00000000...00000000
SRQ - SRD command
0000
SA
SA
SINT
SINT
SD
SD
00000000...00000000
00000000...00000000
00000000...00000000
SCK
CMD
SIO0
SIO1
T
4
T
36
T
20
T
52
T
68
First 3 packets are repeated
from SIO0 to SIO1
non-addressed RDRAMs pass
0/SD15..SD0/0 from SIO1 to SIO0
1
1
1
1
0
0
0
0
1111
next transaction
0
0
controller drives
0 on SIO0
0
0
addressed RDRAM drives
0/SD15..SD0/0 on SIO0
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