參數(shù)資料
型號(hào)： KM416RD4C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司）
文件頁(yè)數(shù)： 32/59頁(yè)
文件大?。?/td> 4654K
代理商： KM416RD4C
Page 33
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
. .
Figure 27 : INIT Register
Figure 28 : CNFGA Register
15 14 13 12 11 10
VID
5
9
8
7
6
5
4
3
2
1
0
Control Register: INIT
Read/write register.
Reset values are undefined except as affected by SIO Reset as noted
below. SETR/CLRR Reset does not affect this register.
SDEVID5..0 - Serial Device Identification. Compared to SDEV5..0
serial address field of serial request packet for register read/write transac-
tions. This determines which RDRAM is selected for the register read or
write operation.
SDEVID resets to 3f
16
.
SDEVID4..SDEVID0
0
SRP PSX
NSR
PSR
LSR
0
PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the
DQA5..0 pins.
SRP - SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0.
SRP resets
to 1.
NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode.
NSR resets to 0.
PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode.
PSR resets to 0.
Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh supply
current is reduced.
LSR resets to 0.
Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit
to be read to determine if a thermal trip point has been exceeded.
TEN resets to 0.
Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0
when it has not. TSQ is available during a current control operation (see Figure 50).
RDRAM Disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permits
normal operation. This mechanism disables an RDRAM.
DIS resets to 0.
Address: 021
16
TEN
TSQ
DIS
15 14 13 12 11 10
PVER5..0
= 000001
9
8
7
6
5
4
3
2
REFBIT2..0
= 000
1
0
Control Register: CNFGA
Address: 023
16
0
0
0
0
0
0
0
0
1
0
Read-only register.
REFBIT2..0 - Refresh Bank Bits. Specifies the number of
high order bank address bits to be ignored during REFA and
REFP commands. Permits multi-bank refresh in future
RDRAMs.
DBL - Doubled-Bank. DBL=1 means the device uses a
doubled-bank architecture with adjacent-bank dependency.
DBL=0 means no dependency.
MVER5..0 - Manufacturer Version. Specifies the manufac-
turer identification number.
PVER5..0 - Protocol Version. Specifies the Direct Protocol
version used by this device:
0 - Compliant with version 0.62 and ECO1-ECO18.
1 - Compliant with version 0.7 and ECO1-ECO38.
2 to 63 - Reserved
DBL
MVER5..0
= mmmmmm
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