參數(shù)資料
型號: KM416RD4C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Direct Rambus DRAM(Direct Rambus 動態(tài)RAM)
中文描述: 直接Rambus公司的DRAM(動態(tài)內(nèi)存直接Rambus公司)
文件頁數(shù): 52/59頁
文件大?。?/td> 4654K
代理商: KM416RD4C
Page 53
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
CMOS - Transmit Timing
Figure Figure is a timing diagram which shows the detailed
requirements for the CMOS output signals. The SIO0 signal
is driven once per t
CYCLE1
interval on the falling edge. The
clock-to-output window is t
Q1,MIN
/t
Q1,MAX.
The SCK and
SIO0 timing points are measured at the 50% level. The rise
and fall times of SIO0 are t
QR1
and t
QF1
, measured at the
20% and 80% levels.
Figure 57 : CMOS Timing - Data Signals for Transmit
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
SCK
SIO0
t
QR1
t
QF1
V
OH,CMOS
50%
V
OL,CMOS
80%
20%
t
Q1,MAX
V
IH,CMOS
50%
V
IL,CMOS
80%
20%
t
Q1,MIN
V
OH,CMOS
50%
V
OL,CMOS
80%
20%
SIO0
or
SIO1
t
DR1
t
DF1
t
QR1
t
QF1
t
PROP1,MAX
t
PROP1,MIN
SIO1
or
SIO0
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