參數(shù)資料
型號(hào)： KM416RD4C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司）
文件頁(yè)數(shù)： 45/59頁(yè)
文件大?。?/td> 4654K
代理商： KM416RD4C
Page 46
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
t
DR2,
t
DF2
CMD, SCK input rise and fall times
-
2.0
ns
Figure Figure
t
CYCLE1
SCK cycle time - Serial control register transactions
1000
-
ns
Figure Figure
SCK cycle time - Power transitions
10
-
ns
Figure Figure
t
CH1
, t
CL1
SCK high and low times
4.25
-
ns
Figure Figure
t
S1
CMD setup time to SCK rising or falling edge
1
-
ns
Figure Figure
t
H1
CMD hold time to SCK rising or falling edge
1
-
ns
Figure Figure
t
S2
SIO0 setup time to SCK falling edge
40
-
ns
Figure Figure
t
H2
SIO0 hold time to SCK falling edge
40
-
ns
Figure Figure
t
S3
PDEV setup time on DQA5..0 to SCK rising edge.
0
-
ns
Figure 47,
Figure Figure
t
H3
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
-
ns
Figure 47,
Figure Figure
t
S4
ROW2..0, COL4..0 setup time for quiet window
-1
-
t
CYCLE
Figure 47
t
H4
ROW2..0, COL4..0 hold time for quiet window
5
-
t
CYCLE
Figure 47
v
IL,CMOS
CMOS input low voltage - over/undershoot voltage duration is
less than or equal to 5ns
- 0.7
V
CMOS
/2 -
0.6
V
v
IH,CMOS
CMOS input high voltage - over/undershoot voltage duration is
less than or equal to 5ns
V
CMOS
/2
+ 0.6
V
CMOS
+
0.7
V
t
NPQ
Quiet on ROW/COL bits during NAP/PDN entry
4
-
t
CYCLE
Figure 46
t
READTOCC
Offset between read data and CC packets (same device)
12
-
t
CYCLE
Figure Figure
t
CCSAMTOREAD
Offset between CC packet and read data (same device)
8
-
t
CYCLE
Figure Figure
t
CE
CTM/CFM stable before NAP/PDN exit
2
-
t
CYCLE
Figure 47
t
CD
CTM/CFM stable after NAP/PDN entry
25
-
t
CYCLE
Figure 46
t
FRM
ROW packet to COL packet ATTN framing delay
7
-
t
CYCLE
Figure 45
t
NLIMIT
Maximum time in NAP mode
10.0
μ
s
Figure 44
t
REF
Refresh interval
32
ms
Figure 49
t
CCTRL
Current control interval
0.0001
100
ms
Figure Figure
t
TEMP
Temperature control interval
100
ms
Figure Figure
t
TCEN
TCE command to TCAL command
4
250
t
CYCLE
Figure Figure
t
TCAL
TCAL command to quiet window
6
6
t
CYCLE
Figure Figure
t
TCQUIET
Quiet window (no read data)
140
-
t
CYCLE
Figure Figure
t
RAS
RAS interval (time a row may stay activated)
64
μ
s
Figure 15
Figure 16
t
PAUSE
RDRAM delay (no RSL operations allowed)
200.0
μ
s
page 28
Table 19 : Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM416RD4D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD8AC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD8AC(D)-RK70 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD8AC(D)-RK80 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD8AC(DB)-RCG60 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
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