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參數(shù)資料
| 型號(hào)： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 57/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
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Page 58
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
This circuit does not include pin coupling effects that are
often present in the packaged device. Because coupling
effects make the effective single-pin inductance L
I
, and
capacitance C
I
, a function of neighboring pins, these param-
eters are intrinsically data-dependent. For purposes of speci-
fying the device electrical loading on the Channel, the
effective L
I
and C
I
are defined as the worst-case values over
all specified operating conditions.
L
I
is defined as the effective pin inductance based on the
device pin assignment. Because the pad assignment places
each RSL signal adjacent to an AC ground (a Gnd or Vdd
pin), the effective inductance must be defined based on this
configuration. Therefore, L
I
assumes a loop with the RSL
pin adjacent to an AC ground.
C
I
is defined as the effective pin capacitance based on the
device pin assignment. It is the sum of the effective package
pin capacitance and the IO pad capacitance.
Table 25 : RSL Pin Parasitics
Symbol
Parameter and Conditions - RSL pins
Min
Max
Unit
L
I
RSL effective input inductance
4.0
nH
L
12
Mutual inductance between any DQA or DQB RSL signals.
0.2
nH
Mutual inductance between any ROW or COL RSL signals.
0.6
nH
C
I
RSL effective input capacitance
a
2.0
2.4
pF
C
12
Mutual capacitance between any RSL signals.
-
0.1
pF
C
I
Difference in C
I
value between any RSL pins of a single device.
-
0.04
pF
R
I
RSL effective input resistance
5
15
a.This value is a combination of the device IO circuitry and package capacitances.
Table 26 : CMOS Pin Parasitics
Symbol
Parameter and Conditions - CMOS pins
Min
Max
Unit
L
I ,CMOS
CMOS effective input inductance
8.0
nH
C
I ,CMOS
CMOS effective input capacitance (SCK,CMD)
a
1.7
2.1
pF
C
I ,CMOS,SIO
CMOS effective input capacitance (SIO1, SIO0)
a
-
7.0
pF
a.This value is a combination of the device IO circuitry and package capacitances.
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