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參數(shù)資料
| 型號： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 28/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
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Page 29
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
Initialization
Initialization refers to the process that a controller must go
through after power is applied to the system or the system is
reset. The controller prepares the RDRAM sub-system for
normal Channel operation by using a sequence of control
register transactions on the serial CMOS pins.
The first step in this sequence is to assign unique serial
device addresses to all the RDRAMs. This is done with
Algorithm InitDev, shown in the opposite column. The
controller assumes that there are no more that “N” RDRAMs
on the Channel (the Channel maximum is 32, but some appli-
cations may have a lower limit).
First, the SIO0 and SIO1 pin directionality is established
with the sequence in step 1. The controller then resets all
RDRAMs, using broadcast SETR and CLRR commands
(steps 2,3,4) with a delay in between (this is also called SIO
Reset). In step 5, a SETF command establishs the normal
clock frequency. See Figure Figure for the format of SETR,
CLRR, and SETF transactions. In step 6 the SIO0-to-SIO1
link is broken in all RDRAMs, so the controller is only
talking to the first RDRAM. Also, the SDEVID field is set to
its maximum value. Next, the loop index INDX is initialized
(step 7). In step 8, the SDEVID field is loaded with the
INDX value, and the SRP bit is set so the next RDRAM
becomes accessible. In step 9, the INDX value is incre-
mented, and in step 10, steps 8 and 9 are repeated for the
remaining RDRAMs.
Finally, it will be necessary for the controller to force a 200
μ
s
pause interval to allow the RDRAM core timing circuits to
stabilize. All banks of all RDRAMs must also be accessed
twice. An access is an activate (ACT) and a precharge (PRE)
command. This may be accomplished with the refresh
commands.
At this point, Algorithm InitDev is complete and all
RDRAMs have a unique device address SDEVID5..0 for
control register transactions. Note that the SDEVID address
value of an RDRAM indicates its position in the daisy-
chained CMOS serial pins. This will not necessarily be the
same value as the DEVID register which is used for memory
transactions. The next steps taken by the controller will vary
depending upon the application, so only a rough outline can
be given here.
=======================================
Algorithm InitDev: Assign SDEVID Device Addresses
1.
Issue SIO Pin Initialization sequence (see Figure Figure).
2.
Issue one SETR transaction:
SOP3..SOP0 = 0010 (SETR command)
SBC = 1 (Broadcast)
SDEV5..SDEV0 = 000000 (don’t care).
3.
Wait 16 SCK cycles.
4.
Issue one CLRR transaction:
SOP3..SOP0 = 0011 (CLRR command)
SBC = 1 (Broadcast)
SDEV5..SDEV0 = 000000 (don’t care).
5.
Wait 4 SCK cycles.
6.
Issue one SETF transaction:
SOP3..SOP0 = 0100 (SETF command)
SBC = 1 (Broadcast)
SDEV5..SDEV0 = 000000 (don’t care).
7.
Issue one register write transaction:
SOP3..SOP0 = 0001 (SWR command)
SBC = 1 (broadcast)
SDEV5..SDEV0 = 000000 (don’t care).
SA11..SA0 = 021
16
(INIT control register).
SD15..SD0 = 401f
16
(SRP<=0, SDEVID<=3f).
8.
Set INDX5..INDX0 to 000000
2
. INDX is a counter in the
Controller which acts as a loop index.
9.
Issue one register write transaction (SRP<=1, SDEVID<=INDX):
SOP3..SOP0 = 0001 (SWR command)
SBC = 0 (non-broadcast)
SDEV5..SDEV0 = 111111.
SA11..SA0 = 021
16
(INIT control register).
SD15..SD0 = {0
2
, INDX5, 00000100
2
, INDX4..INDX0}.
10.
Increment INDX5..INDX0.
11.
Repeat Steps (8) and (9) an additional (N-1) times.
12.
t
PAUSE
delay, then t
PDNXA
+ t
PDNXB
delay (to allow DLLs to lock),
then access all banks twice (i.e. 32xREFA/REFP).
Figure 26 : SIO Reset Sequence
SCK
CMD
SIO0
T
16
0000000000000000
00000000...00000000
0000000000000000
1100
SIO1
T
0
The packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
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