參數(shù)資料
型號(hào): KM416RD4C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述: 直接Rambus公司的DRAM(動(dòng)態(tài)內(nèi)存直接Rambus公司)
文件頁(yè)數(shù): 33/59頁(yè)
文件大?。?/td> 4654K
代理商: KM416RD4C
Page 34
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
. .
Figure 29 : CNFGB Register
15 14 13 12 11 10
SVER5..0
= ssssss
9
8
7
6
5
4
3
DEVTYP2..0
= 000
2
1
0
Control Register: CNFGB
Address: 024
16
0
0
0
0
0
0
0
0
0
0
B
Read-only register.
BYT - Byte width. B=1 means the device reads and
writes 9-bit memory bytes. B=0 means 8 bits.
DEVTYP2..0 - Device type. DEVTYP = 000 means
that this device is an RDRAM.
BYT
CORG4..0
= xxxxx
SPT
SPT - Split-core. SPT=1 means the core is split, SPT=0 means it is not.
CORG4..0 - Core organization. This field specifies the number of bank (3,
4, 5, or 6 bits), row (9, 10, 11, or 12 bits), and column (5, 6, or 7 bits)
address bits. The encoding of this field will be specified in a later version of
this document.
SVER5..0 - Stepping version. Specifies the mask version number of this
device.
Figure 30 : TEST Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value of TEST34 is zero (from SIO Reset)
This register are used for testing purposes. It must not
be read or written after SIO Reset.
Control Register: TEST34
Address: 022
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 31 : DEVID Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined.
Device Identification register.
DEVID4..DEVID0 is compared to DR4..DR0,
DC4..DC0, and DX4..DX0 fields for all memory read
or write transactions. This determines which RDRAM
is selected for the memory read or write transaction.
Control Register: DEVID
Address: 040
16
0
DEVID4..DEVID0
0
0
0
0
0
0
0
0
0
0
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