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參數(shù)資料
| 型號： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 49/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
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Page 50
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
RSL - Transmit Timing
Figure Figure is a timing diagram which shows the detailed
requirements for the RSL output signals on the Channel.
The DQA and DQB signals are outputs to transmit informa-
tion that is received by a Direct RAC on the Channel. Each
signal is driven twice per t
CYCLE
interval. The beginning
and end of the even transmit window is at the 75% point of
the previous cycle and at the 25% point of the current cycle.
The beginning and end of the odd transmit window is at the
25% point and at the 75% point of the current cycle. These
transmit points are measured relative to the crossing points
of the falling CTM clock edge. The size of the actual
transmit window is less than the ideal t
CYCLE
/2, as indicated
by the non-zero values of t
Q,MIN
and t
Q,MAX
. The t
Q
param-
eters are measured at the V
REF
voltage point of the output
transition.
The t
QR
and t
QF
rise- and fall-time parameters are measured
at the 20% and 80% points of the output transition.
Figure 54 : RSL Timing - Data Signals for Transmit
t
Q,MIN
t
Q,MAX
t
Q,MAX
t
Q,MIN
0.25t
CYCLE
V
QH
V
REF
V
QL
80%
20%
V
CIH
50%
V
CIL
80%
20%
CTM
CTMN
t
QF
t
QR
even
odd
0.75t
CYCLE
0.75t
CYCLE
DQA
DQB
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