參數(shù)資料
型號(hào): KM416RD4C
廠(chǎng)商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述: 直接Rambus公司的DRAM(動(dòng)態(tài)內(nèi)存直接Rambus公司)
文件頁(yè)數(shù): 35/59頁(yè)
文件大小: 4654K
代理商: KM416RD4C
Page 36
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
.
Figure 36 : NAPX Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Control Register: NAPX
Address: 045
16
Read/write register.
Reset value is undefined
NAPXA4..0 - Nap Exit Phase A. This field specifies
the number of SCK cycles during the first phase for
exiting NAP mode. It must satisfy:
NAPXAt
SCYCLE
> t
NAPXA,MAX
Do not set this field to zero.
0
0
0
0
0
DQS
NAPXA4..0
NAPX4..0
NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK
cycles during the first plus second phases for exiting NAP mode. It must satisfy:
NAPXt
SCYCLE
> t
NAPXA,MAX
+t
NAPXB,MAX
Do not set this field to zero.
DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5
cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device
selection on DQ5..0.
Figure 37 : PDNXA Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined
PDNXA4..0 - PDN Exit Phase A. This field specifies
the number of (64SCK cycle) units during the first
phase for exiting PDN mode. It must satisfy:
PDNXA64t
SCYCLE
> t
PDNXA,MAX
Do not set this field to zero.
Note - only PDNXA5..0 are implemented.
Control Register: PDNXA
Address: 046
16
0
0
0
PDNXA12..0
Figure 38 : PDNX Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined
PDNX4..0 - PDN Exit Phase A plus B. This field spec-
ifies the number of (256SCK cycle) units during the
first plus second phases for exiting PDN mode. It must
satisfy:
PDNX256t
SCYCLE
> t
PDNXA,MAX
+t
PDNXB,MAX
Do not set this field to zero.
Note - only PDNX2..0 are implemented.
Control Register: PDNX
Address: 047
16
0
0
0
PDNX12..0
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