參數(shù)資料
型號(hào): KM416RD4C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述: 直接Rambus公司的DRAM(動(dòng)態(tài)內(nèi)存直接Rambus公司)
文件頁(yè)數(shù): 46/59頁(yè)
文件大小: 4654K
代理商: KM416RD4C
Page 47
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
Electrical Characteristics
Timing Characteristics
Table 20 : Electrical Characteristics
Symbol
Parameter and Conditions
Min
Max
Unit
Θ
JC
Junction-to-Case thermal resistance
TBD
°
C/Watt
I
REF
V
REF
current @ V
REF,MAX
-10
10
μ
A
I
OH
RSL output high current @ (0
V
OUT
V
DD
)
-10
10
μ
A
I
ALL
RSL I
OL
current @ V
OL
= 0.9V, V
DD,MIN
, T
J,MAXa
30.0
90.0
mA
I
OL
RSL I
OL
current resolution step
-
1.5
mA
r
OUT
Dynamic output impedance
150
-
I
I,CMOS
CMOS input leakage current @ (0
V
I,CMOS
V
CMOS
)
-10.0
10.0
μ
A
V
OL,CMOS
CMOS output voltage @ I
OL,CMOS
= 1.0mA
-
0.3
V
V
OH,CMOS
CMOS output high voltage @ I
OH,CMOS
= -0.25mA
V
CMOS
-0.3
-
V
a.This measurement is made in manual current control mode; i.e. with all output device legs sinking current.
Table 21 : Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
t
Q
CTM-to-DQA/DQB output time
@ t
CYCLE
=2.5ns
@ t
CYCLE
=3.3ns
-0.30
-0.40
+0.30
+0.40
ns
Figure Fig
ure
t
QR
, t
QF
DQA/DQB output rise and fall times
0.2
0.45
ns
Figure Fig
ure
t
Q1
SCK-to-SIO0 delay @ C
LOAD,MAX
= 20pF (SD read packet).
-
10
ns
Figure Fig
ure
t
QR1
, t
QF1
SIO
OUT
rise/fall @ C
LOAD,MAX
= 20pF
-
5
ns
Figure Fig
ure
t
PROP1
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C
LOAD,MAX
= 20pF
-
10
ns
Figure Fig
ure
t
NAPXA
NAP exit delay - phase A
-
50
ns
Figure 47
t
NAPXB
NAP exit delay - phase B
-
40
ns
Figure 47
t
PDNXA
PDN exit delay - phase A
-
4
μ
s
Figure 47
t
PDNXB
PDN exit delay - phase B
-
8
μ
s
Figure 47
t
AS
ATTN-to-STBY power state delay
1
4
t
CYCLE
Figure 45
t
SA
STBY-to-ATTN power state delay
-
3
t
CYCLE
Figure 45
t
ASN
ATTN/STBY-to-NAP power state delay
-
8
t
CYCLE
Figure 46
t
ASP
ATTN/STBY-to-PDN power state delay
-
8
t
CYCLE
Figure 46
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