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參數(shù)資料
| 型號(hào)： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 34/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
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Page 35
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
Figure 32 : REFB Register
Figure 33 : CCA Register
Figure 34 : REFR Register
Figure 35 : CCB Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is zero (from SETR/CLRR).
Refresh Bank register.
REFB3..REFB0 is the bank that will be refreshed next
during self-refresh. REFB3..0 is incremented after each
self-refresh activate and precharge operation pair.
Control Register: REFB
Address: 041
16
0
0
0
0
0
0
0
0
0
0
0
0
REFB3..REFB0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is zero (SETR/CLRR or SIO Reset).
CCA6..CCA0 - Current Control A. Controls the I
OL
output current for the DQA8..DQA0 pins.
ASYMB1,ASYMB0 control the asymmetry of the
V
OL
/V
OH
voltage swing about the V
REF
reference
voltage for the DQA8..0 pins.
Control Register: CCA
Address: 043
16
0
0
0
0
0
0
0
CCA6..CCA0
ASYMA
1..0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is zero (from SETR/CLRR).
Refresh Row register.
REFR8..REFR0 is the row that will be refreshed next
by the REFP command or by self-refresh. REFR8..0 is
incremented when BR3..0=1111 for the REFA
command. REFR8..0 is incremented when
REFB3..0=1111 for self-refresh.
Control Register: REFR
Address: 042
16
0
0
0
0
0
0
0
REFR8..REFR0
15 14 13 12 11 10
9
8
ASYMB
7
6
5
4
3
2
1
0
Read/write register.
Reset value is zero (SETR/CLRR or SIO Reset).
CCB6..CCB0 - Current Control B. Controls the I
OL
output current for the DQB8..DQB0 pins.
ASYMB1,ASYMB0 control the asymmetry of the
V
OL
/V
OH
voltage swing about the V
REF
reference
voltage for the DQB8..0 pins.
Control Register: CCB
Address: 044
16
0
0
0
0
0
0
0
CCB6..CCB0
1..0
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