參數(shù)資料
型號(hào)： KM416RD4C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司）
文件頁(yè)數(shù)： 27/59頁(yè)
文件大?。?/td> 4654K
代理商： KM416RD4C
Page 28
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
Control Register Packets
Table Table summarizes the formats of the four packet types
for control register transactions. Table Table summarizes the
fields that are used within the packets.
Figure Figure shows the transaction format for the SETR,
CLRR, and SETF commands. These transactions consist of a
single SRQ packet, rather than four packets like the SWR
and SRD commands. The same framing sequence on the
CMD input is used, however. These commands are used
during initialization prior to any control register read or
write transactions.
Figure 25 : SETR, CLRR,SETF Transaction
SCK
CMD
SIO0
T
20
SRQ packet - SETR/CLRR/SETF
1111
00000000...00000000
SRQ packet - SETR/CLRR/SETF
0000
SIO1
T
4
The packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
Table 14 : Control Register Packet Formats
SCK
Cycle
SIO0 or
SIO1
for SRQ
SIO0 or
SIO1
for SA
SIO0 or
SIO1
for SINT
SIO0 or
SIO1
for SD
SCK
Cycle
SIO0 or
SIO1
for SRQ
SIO0 or
SIO1
for SA
SIO0 or
SIO1
for SINT
SIO0 or
SIO1
for SD
0
rsrv
rsrv
0
SD15
8
SOP1
SA7
0
SD7
1
rsrv
rsrv
0
SD14
9
SOP0
SA6
0
SD6
2
rsrv
rsrv
0
SD13
10
SBC
SA5
0
SD5
3
rsrv
rsrv
0
SD12
11
SDEV4
SA4
0
SD4
4
rsrv
SA11
0
SD11
12
SDEV3
SA3
0
SD3
5
SDEV5
SA10
0
SD10
13
SDEV2
SA2
0
SD2
6
SOP3
SA9
0
SD9
14
SDEV1
SA1
0
SD1
7
SOP2
SA8
0
SD8
15
SDEV0
SA0
0
SD0
Table 15 : Field Description for Control Register Packets
Field
Description
rsrv
Reserved. Should be driven as “0” by controller.
SOP3..SOP0
0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0010 - SETR. Set Reset bit, all control registers assume their reset values.
a
16 t
SCYCLE
delay until CLRR command.
0100 - SETF. Set fast (normal) clock mode.
1011 - CLRR. Clear Reset bit, all control registers retain their reset values.
a
4 t
SCYCLE
delay until next command.
1111 - NOP. No serial operation.
0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings.
SDEV5..SDEV0
Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to which the transac-
tion is directed.
SBC
Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection.
SA11..SA0
Serial address. Selects which control register of the selected RDRAM is read or written.
SD15..SD0
Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.
a.The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called “SETR/CLRR Reset”.
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