- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374354 > KM416RD4C (SAMSUNG SEMICONDUCTOR CO. LTD.) Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | KM416RD4C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Direct Rambus DRAM(Direct Rambus 動態(tài)RAM) |
| 中文描述： | 直接Rambus公司的DRAM（動態(tài)內(nèi)存直接Rambus公司） |
| 文件頁數(shù)： | 36/59頁 |
| 文件大?。?/td> | 4654K |
| 代理商： | KM416RD4C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
Page 37
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
.
Figure 39 : TPARM Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined.
TCAS1..0 - Specifies the t
CAS-C
core parameter in
t
CYCLE
units. This should be “10” (2t
CYCLE
).
TCLS1..0 - Specifies the t
CLS-C
core parameter in
t
CYCLE
units. Should be “10” (2t
CYCLE
).
TCDLY0 - Specifies the t
CDLY0-C
core parameter in
t
CYCLE
units. This adds a programmable delay to Q
(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
with the values “010” (2t
CYCLE
) through “101”
(5t
CYCLE
).
Control Register: TPARM
Address: 048
16
0
0
0
0
0
0
0
0
0
0
0
TCAS
TCLS
The equations relating the core parameters to the
datasheet parameters follow:
t
CAS-C
= 2t
CYCLE
t
CLS-C
= 2t
CYCLE
t
CPS-C
= 1t
CYCLE
t
OFFP
= t
CPS-C
+ t
CAS-C
+ t
CLS-C
- 1t
CYCLE
= 4t
CYCLE
Not programmable
t
RCD
= t
RCD-C
+ 1t
CYCLE
- t
CLS-C
= t
RCD-C
- 1t
CYCLE
t
CAC
= 3t
CYCLE
+ t
CLS-C
+ t
CDLY0-C
+ t
CDLY1-C
(see table below for programming ranges)
TCDLY0
011
011
101
100
TCDLY0
010
010
3t
CYCLE
3t
CYCLE
5t
CYCLE
4t
CYCLE
t
CDLY0-C
3t
CYCLE
2t
CYCLE
010
001
010
010
TCDLY1
000
000
2t
CYCLE
1t
CYCLE
2t
CYCLE
2t
CYCLE
t
CDLY1-C
0t
CYCLE
0t
CYCLE
10t
CYCLE
9t
CYCLE
not allowed
11t
CYCLE
t
CAC
@ t
CYCLE
= 3.3ns
8t
CYCLE
7t
CYCLE
10t
CYCLE
9t
CYCLE
12t
CYCLE
11t
CYCLE
t
CAC
@ t
CYCLE
= 2.5ns
8t
CYCLE
not allowed
Figure 40 : TFRM Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in t
CYCLE
units. This value must be greater than or
equal to the t
FRM,MIN
parameter. This is the minimum
offset between a ROW packet (which places a device at
ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
written with the values “0111” (7t
CYCLE
) through
“1010” (10t
CYCLE
). TFRM is usually set to the value
which matches the largest t
RCD,MIN
parameter (modulo
4t
CYCLE
) that is present in an RDRAM in the memory
system. Thus, if an RDRAM with t
RCD,MIN
=
11t
CYCLE
were present, then TFRM would be
programmed to 7t
CYCLE
.
Control Register: TFRM
Address: 049
16
0
0
0
0
0
0
0
0
0
0
0
0
TFRM3..0
Figure 41 : TRDLY Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the t
CDLY1-C
core
parameter in t
CYCLE
units. This adds a programmable
delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values “000” (0t
CYCLE
) through
“010” (2t
CYCLE
). Refer to Figure Figure for more
details.
Control Register: TCDLY1
Address: 04a
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCDLY1
相關PDF資料 |
PDF描述 |
|---|---|
| KM416S1021CT-G7 | 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface |
| KM416S1021CT-G8 | 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface |
| KM416S1021CT-GS | 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface |
| KM416S1120D | 512K x 16bit x 2 Banks Synchronous DRAM LVTTL |
| KM416S16230A | 4M x 16Bit x 4 Banks Synchronous DRAM(4M x 16位 x4組同步動態(tài)RAM) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KM416RD4D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(D)-RK70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(D)-RK80 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM416RD8AC(DB)-RCG60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
發(fā)布緊急采購，3分鐘左右您將得到回復。