參數(shù)資料
型號(hào)： KM416RD4C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司）
文件頁數(shù)： 53/59頁
文件大小： 4654K
代理商： KM416RD4C
Page 54
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.7 September 1998
TARGET
Figure Figure also shows the combinational path connecting
SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read
data only). The t
PROP1
parameter specified this propagation
delay. The rise and fall times of SIO0 and SIO1 inputs must
be t
DR1
and t
DF1
, measured at the 20% and 80% levels. The
rise and fall times of SIO0 and SIO1 outputs are t
QR1
and
t
QF1
, measured at the 20% and 80% levels.
RSL - Domain Crossing Window
When read data is returned by the RDRAM, imformation
must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The t
TR
parameter permits
the CFM to CTM phase to vary through an entire cycle; i.e.
there is no restriction on the alignment of these two clocks.
A second parameter t
DCW
is needed in order to describe how
the delay between a RD command packet and read data
packet varies as a function of the t
TR
value.
Figure Figure shows this timing for five distinct values of
t
TR
. Case A (t
TR
=0) is what has been used throughout this
document. The delay between the RD command and read
data is t
CAC
. As t
TR
varies from zero to t
CYCLE
(cases A
through E), the command to data delay is (t
CAC
-t
TR
). When
the t
TR
value is in the range 0 to t
DCW,MAX
, the command to
data delay can also be (t
CAC
-t
TR
-t
CYCLE
). This is shown as
cases A’ and B’ (the gray packets). Similarly, when the t
TR
value is in the range (t
CYCLE
+t
DCW,MIN
) to t
CYCLE
, the
command to data delay can also be (t
CAC
-t
TR
+t
CYCLE
). This
is shown as cases D’ and E’ (the gray packets). The
RDRAM will work reliably with either the white or gray
packet timing. The delay value is selected at initialization,
and remains fixed thereafter.
Figure 58 : RSL Transmit - Crossing Read Domains
CFM
COL
t
TR
CTM
DQA/B
DQA/B
t
TR
=0
t
CYCLE
Case A
t
TR
=0
Case A’
t
TR
CTM
DQA/B
DQA/B
t
TR
=t
DCW,MAX
Case B
t
TR
=t
DCW,MAX
Case B’
t
TR
CTM
DQA/B
t
TR
=0.5t
CYCLE
Case C
CTM
DQA/B
DQA/B
t
TR
=t
CYCLE
+t
DCW,MIN
Case D
t
TR
=t
CYCLE
+t
DCW,MIN
Case D’
CTM
DQA/B
DQA/B
t
TR
=t
CYCLE
Case E
t
TR
=t
CYCLE
Case E’
t
TR
t
TR
RD a1
Q(a1)
Q(a1)
Q(a1)
Q(a1)
t
CAC
-t
TR
t
CAC
-t
TR
-t
CYCLE
Q(a1)
Q(a1)
Q(a1)
Q(a1)
Q(a1)
t
CAC
-t
TR
t
CAC
-t
TR
+t
CYCLE
t
CAC
-t
TR
t
CAC
-t
TR
+t
CYCLE
t
CAC
-t
TR
t
CAC
-t
TR
-t
CYCLE
t
CAC
-t
TR
相關(guān)PDF資料
PDF描述
KM416S1021CT-G7 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
KM416S1021CT-G8 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
KM416S1021CT-GS 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
KM416S1120D 512K x 16bit x 2 Banks Synchronous DRAM LVTTL
KM416S16230A 4M x 16Bit x 4 Banks Synchronous DRAM(4M x 16位 x4組同步動(dòng)態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM416RD4D 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD8AC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD8AC(D)-RK70 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD8AC(D)-RK80 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM416RD8AC(DB)-RCG60 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
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