參數(shù)資料
型號(hào)： KM416RD4C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： Direct Rambus DRAM(Direct Rambus 動(dòng)態(tài)RAM)
中文描述： 直接Rambus公司的DRAM（動(dòng)態(tài)內(nèi)存直接Rambus公司）
文件頁(yè)數(shù)： 30/59頁(yè)
文件大?。?/td> 4654K
代理商： KM416RD4C
Page 31
KM416RD4C/KM418RD4C
Direct RDRAM
Revision 0.2 September 1998
TARGET
Control Register Summary
Table Table summarizes the RDRAM control registers.
Detail is provided for each control register in Figure Figure
through Figure 43. Read-only bits which are shaded gray are
unused and return zero. Read-write bits which are shaded
gray are reserved and should always be written with zero.
The RIMM SPD Application Note (DL-0054) describes
additional read-only configuration registers which are
present on Direct RIMMs.
The state of the register fields are potentially affected by the
IO Reset operation or the SETR/CLRR operation. This is
indicated in the text accompanying each register diagram.
Table 16 : Control Register Summary
SA11..SA0
Register
Field
read-write/ read-only
Description
021
16
INIT
SDEVID
read-write, 6 bits
Serial device ID. Device address for control register read/write.
PSX
read-write, 1 bit
Power select exit. PDN/NAP exit with device addr on DQA5..0.
SRP
read-write, 1 bit
SIO repeater. Used to initialize RDRAM.
NSR
read-write, 1 bit
NAP self-refresh. Enables self-refresh in NAP mode.
PSR
read-write, 1 bit
PDN self-refresh. Enables self-refresh in PDN mode.
LSR
read-write, 1 bit
Low power self-refresh. Enables low power self-refresh.
TEN
read-write, 1 bit
Temperature sensing enable. Enables low power self-refresh.
TSQ
read-write, 1 bit
Temperature sensing output. Enables low power self-refresh.
DIS
read-write, 1 bit
RDRAM disable.
022
16
TEST34
TEST34
read-write, 16 bits
Test register. Do not read or write after SIO reset.
023
16
CNFGA
REFBIT
read-only, 3 bit
Refresh bank bits. Used for multi-bank refresh.
DBL
read-only, 1 bit
Double. Specifies doubled-bank architecture
MVER
read-only, 6 bit
Manufacturer version. Manufacturer identification number.
PVER
read-only, 6 bit
Protocol version. Specifies version of Direct protocol supported.
024
16
CNFGB
BYT
read-only, 1 bit
Byte. Specifies an 8-bit or 9-bit byte size.
DEVTYP
read-only, 3 bit
Device type. Device can be RDRAM or some other device category.
CORG
read-only, 6 bit
Core organization. Bank, row, column address field sizes.
SVER
read-only, 6 bit
Stepping version. Mask version number.
040
16
DEVID
DEVID
read-write, 5 bits
Device ID. Device address for memory read/write.
041
16
REFB
REFB
read-write, 4 bits
Refresh bank. Next bank to be refreshed by self-refresh.
042
16
REFR
REFR
read-write, 9 bits
Refresh row. Next row to be refreshed by REFA, self-refresh.
043
16
CCA
CCA
read-write, 7 bits
Current control A. Controls I
OL
output current for DQA.
ASYMA
read-write, 2 bits
Asymmetry control. Controls asymmetry of V
OL
/V
OH
swing for DQA.
044
16
CCB
CCB
read-write, 7 bits
Current control B. Controls I
OL
output current for DQB.
ASYMB
read-write, 2 bits
Asymmetry control. Controls asymmetry of V
OL
/V
OH
swing for DQB.
045
16
NAPX
NAPXA
read-write, 5 bits
NAP exit. Specifies length of NAP exit phase A.
NAPX
read-write, 5 bits
NAP exit. Specifies length of NAP exit phase A + phase B.
DQS
read-write, 1 bits
DQ select. Selects CMD framing for NAP/PDN exit.
046
16
PDNXA
PDNXA
read-write, 13 bits
PDN exit. Specifies length of PDN exit phase A.
047
16
PDNX
PDNX
read-write, 13 bits
PDN exit. Specifies length of PDN exit phase A + phase B.
048
16
TPARM
TCAS
read-write, 2 bits
t
CAS-C
core parameter. Determines t
OFFP
datasheet parameter.
TCLS
read-write, 2 bits
t
CLS-C
core parameter. Determines t
CAC
and t
OFFP
parameters.
TCDLY0
read-write, 3 bits
t
CDLY0-C
core parameter. Programmable delay for read data.
049
16
TFRM
TFRM
read-write, 4 bits
t
FRM-C
core parameter. Determines ROW-COL packet framing interval.
04a
16
TCDLY1
TCDLY1
read-write, 3 bits
t
CDLY1-C
core parameter. Programmable delay for read data.
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