Data Sheet
July 2000
DSP16210 Digital Signal Processor
104
DRAFT COPY
Lucent Technologies Inc.
Software Architecture
(continued)
Registers
(continued)
Register Settings
(continued)
Table 63. PHIFC (PHIF16 Control) Register
Note:
This register is not directly program-accessible. It must be programmed through MIOU0 by writing
mcmd0
.
11—8
7
6
5
Reserved
PCFIG
PSOBEF
PFLAGSEL
4
3
2
1
0
PFLAG
PBSELF
PSTRB
PSTROBE
PMODE
Bit
11—8
7
Field
Reserved
PCFIG
Value
—
0
1
0
1
0
1
Description
Reserved—write with zero.
8-bit external bus configuration. PB[15:8] are 3-stated.
16-bit external bus configuration.
POBE flag as read through PSTAT register is active-high.
POBE flag as read through PSTAT register is active-low.
The state of the PIBF pin is same as that of the PIBF flag.
The state of the PIBF pin is the PIBF flag logically ORed with the POBE flag. (The
state of the POBE pin is unaffected and is the same as that of the POBE flag.)
PIBF and POBE pins active-high.
PIBF and POBE pins active-low.
If PMODE = 0, PBSEL pin = 0 –> PDX0 low byte.
If PMODE = 1, PBSEL pin = 0 –> PDX0 low byte.
If PMODE = 1, PBSEL pin = 1 –> PDX0 high byte.
If PMODE = 0, PBSEL pin = 1 –> PDX0 low byte.
If PMODE = 1, PBSEL pin = 0 –> PDX0 high byte.
If PMODE = 1, PBSEL pin = 1 –> PDX0 low byte.
If PSTROBE = 1, PODS pin (PDS) active-low.
If PSTROBE = 1, PODS pin (PDS) active-high.
Intelprotocol: PIDS and PODS data strobes.
Motorolaprotocol: PRWN and PDS data strobes.
If 8-bit external bus configuration, 8-bit logical data transfers.
If 16-bit external bus configuration, preserve high and low byte positions.
If 8-bit external bus configuration, 16-bit logical data transfers.
If 16-bit external bus configuration, swap high and low byte positions.
6
PSOBEF
5
PFLAGSEL
4
PFLAG
0
1
0
3
PBSELF
1
2
PSTRB
0
1
0
1
0
1
PSTROBE
0
PMODE
1