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參數資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數字信號處理器 |
| 文件頁數： | 58/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
58
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Clock Synthesis
(continued)
The clock switch module (the SYNC MUX blocks
shown in
Figure 19 on page 57
) selects the clock
source synchronously for glitch-free operation. Poten-
tial clock sources are first synchronized to the current
CLK before being prioritized and acted upon by the
clock switch module.
Phase-Lock Loop (PLL) Operation
Because
pllc
is cleared on reset, the PLL is initially
deselected and powered down. For the PLL to oper-
ate, the following is required:
1. A clock must be applied to the CKI input pin, the
input to the PLL.
2. The program must enable (power up) the PLL by set-
ting the PLLEN bit (
pllc
bit 15). (Clearing PLLEN
disables (powers down) the PLL.) The program
must not select the PLL, i.e., must not set the
PLLSEL bit (
pllc
bit 14), until the LOCK flag is set as
described later in this section. The programming of
the remaining bits of
pllc
and the frequency of CKI
determine the frequency of the PLL output.
Phase-Lock Loop (PLL) Operating Frequency
The frequency of the PLL output clock (f
PLL
) is deter-
mined by the values loaded into the 3-bit N divider and
the 5-bit M divider as follows:
f
PLL
= f
CKI
×
M/2N
where 2
≤
M
≤
24 and 1
≤
N
≤
8. The maximum allow-
able M/N ratio is 12. If the PLL is selected as the clock
source, the frequency of the internal clock (CLK) is:
f
CLK
=
f
PLL
= f
CKI
×
M/2N
The following requirements apply to the f
PLL
:
I
f
PLL
≥
f
CKI
.
I
f
PLL
must fall within the range defined in
Table 87 on
page 139
. (f
CLK
must not exceed the maximum
instruction rate defined in
Table 83 on page 133
).
After choosing f
PLL
and f
CKI
, choose the lowest value for
N and the appropriate value of M to obtain the desired
frequency. Program M and N into the Mbits[4:0] and
Nbits[2:0] fields (
pllc
[4:0] and
pllc
[7:5]) as follows:
Mbits[4:0] = M – 2
if (N==1)
Nbits[2:0] = 0x7
else
Nbits[2:0] = N – 2
The results of these formulas are summarized in
Table 29
:
Table 29. pllc Field Values Nbits[2:0] and Mbits[2:0]
N
Nbits[2:0]
1
7
111
2
0
000
3
1
001
4
2
010
5
3
011
6
4
100
7
5
101
8
6
110
Program the loop filter field LF[3:0] (
pllc
[11:8]) accord-
ing to
Table 88 on page 139
.
Phase-Lock Loop (PLL) Locking
Before selecting the PLL as the clock source, the pro-
gram must ensure that the PLL has stabilized and
locked to the programmed frequency. The DSP16210
indicates that the PLL has locked by setting the LOCK
flag (see
Table 37 on page 85
and
alf
register bit 6 in
Table 42 on page 91
). Once the program has checked
that the LOCK flag is set, it can then safely set PLLSEL
(
pllc
bit 14) to switch sources from f
CKI
to f
PLL
without
glitching. If LOCK is cleared, the PLL output is unsta-
ble. Every time the program writes
pllc
, the LOCK flag
is cleared. The LOCK flag status is tested by condi-
tional instructions that have the qualifier
if lock
, e.g.,
if lock goto pll_select
. The typical lock-in time is
specified in
Table 88 on page 139
.
Before removing the clock from the clock input pin
(CKI), the program must first deselect and power down
the PLL (PLLSEL = 0 and PLLEN = 0). Otherwise, the
LOCK flag is not cleared, and when the input clock is
reapplied it cannot be determined when the PLL has
stabilized.
M
2
3
4
5
6
Mbits[4:0]
0
1
2
3
4
00000
00001
00010
00011
00100
24
22
10110
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