參數(shù)資料
型號: DSP16210
英文描述: TVS 400W 6.5V UNIDIRECT SMA
中文描述: DSP16210數(shù)字信號處理器
文件頁數(shù): 79/173頁
文件大?。?/td> 2621K
代理商: DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
79
Software Architecture
(continued)
Instruction Set Quick Reference
(continued)
Table 34. Overall Replacement Table
(continued)
IM12
control
12-bit signed immediate value
(–2048 to +2047)
PC-relative near address for
goto
and
call
instruc-
tions.
Postmodification to a general YAAU pointer register to
form address for data move.
Added to the value of a general YAAU pointer register,
and the result is stored into any YAAU register.
Offset for conditional PC-relative
goto/call
instruc-
tions.
Operand for ALU or BMU operation.
Absolute (unsigned) far address for
goto
and
call
instructions. For data move instructions, the
signed/unsigned status of the IM20 value matches
that of the destination register of the assignment
instruction.
For the
do K {N_INSTR}
and
redo K
cache instruc-
tions.
40-bit ALU operation.
data move
and
pointer
arithmetic
control
IM16
16-bit signed immediate value
(–32,768 to +32,767)
F3, F4
control,
data move
IM20
20-bit unsigned immediate value
(0 to 1,048,576)
20-bit signed immediate value
(–524,288 to 524,287)
K
N
OP
cache
1 to 127 or the value in
cloop
1 to 31
+
,
,
&
,
|
, or
^
F1, F1E, F3,
F3E
F2E, F3,
F3E
F1E, control,
data move
data move
pE
p0
or
p1
One of the product registers as source for a special
function or ALU operation.
One of the two XAAU pointer registers as address for
an XE memory access (see XE entry in this table).
One of the main set of core registers that is specified
as the source or destination of a data move operation.
The subscripts are used to indicate that two different
registers can be specified, e.g.,
RA
D
= RA
S
describes
a register-to-register move instruction where RA
D
and
RA
S
are, in general, two different registers.
One of the secondary set of registers that is specified
as the source or destination of a data move operation.
This set includes core and off-core registers.
ptE
pt0
or
pt1
RA
RA
D
RA
S
a0
,
a1
,
a2
,
a3
,
a4
,
a5
,
a6
,
a7
,
a0h
,
a1h
,
a2h
,
a3h
,
a4h
,
a5h
,
a6h
,
a7h
,
a0l
,
a1l
,
a2l
,
a3l
,
a4l
,
a5l
,
a6l
,
a7l
,
alf
,
auc0
,
c0
,
c1
,
c2
,
h
,
i
,
j
,
k
,
p0
,
p0h
,
p0l
,
p1
,
p1h
,
p1l
,
pr
,
psw0
,
pt0
,
pt1
,
r0
,
r1
,
r2
,
r3
,
r4
,
r5
,
r6
,
r7
,
rb0
,
rb1
,
re0
,
re1
,
sp
,
x
,
xh
,
xl
,
y
,
yh
,
or
yl
core
a0g
,
a1g
,
a2g
,
a3g
,
a4g
,
a5g
,
a6g
,
a7g
,
a0_1h
,
a2_3h
,
a4_5h
,
a6_7h
,
ar0
,
ar1
,
ar2
,
ar3
,
auc1
,
cloop
,
cstate
,
csave
,
inc0
,
inc1
,
ins
,
pi
,
psw1
,
ptrap
,
vbase
,
or vsw
off-core
cbit
,
ioc
,
jiob
,
mcmd0
,
mcmd1
,
miwp0
,
miwp1
,
morp0
,
morp1
,
mwait
,
pllc
,
powerc
,
sbit
,
timer0
,
timer0c
,
timer1
, or
timer1c
Any of the RA or RB registers
(see rows above)
RB
RAB
RAB
D
RAB
S
Any one of the registers in the main (RA) or second-
ary (RB) sets of registers that is specified as the
source or destination of a data move operation. The
subscripts are used to indicate that two different regis-
ters can be specified.
Any core register that is specified as the source or
destination of a data move operation.
One of four general YAAU pointer registers used for a
Y memory access (see Y entry in this table).
RC
Any of the RA registers or any of the core RB
registers (see rows above)
r0
,
r1
,
r2
, or
r3
rM
F1,
data move
Symbol
Used in
Instruction
Type(s)
Replaced By
Description
The size of the transfer (single- or double-word) depends on the size of the register on the other side of the equal sign.
These postmodification options are not available for a double-word load except for a load of an accumulator vector.
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