參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 137/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
137
Electrical Characteristics and Requirements
(continued)
Power Dissipation
Power dissipation is highly dependent on DSP program activity and the frequency of operation. The typical power
dissipation listed is for a selected application.
The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the
basis of the application by adding C x V
DD
2
x f for each output, where C is the additional load capacitance and f is
the output frequency. Power dissipation due to the input buffers is highly dependent on the input voltage level. At full
CMOS levels, essentially no dc current is drawn. However, for levels between the power supply rails, especially at
or near the threshold of V
DD
/2, high currents can flow.
The following recommendations apply:
Input and I/O buffers can be left untied with no power dissipation penalty because the input voltage levels of the
input and I/O buffers are designed to remain at full CMOS levels when not driven.
Unused I/O pins that require a known value (1 or 0) for correct device operation should be tied to V
DD
or
V
SS
through a 10 k
resistor.
Unused input pins that require a known value (1 or 0) should be tied to V
DD
or
V
SS
.
WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup.
Otherwise, high currents might flow.
Table 86. Power Dissipation
Condition
In all cases, V
DD
= V
DDA
= 3.0 V, unused inputs are tied to V
DD
or V
SS
, and the CKO output pin is held low (
ioc
= 0x0040).
The PLL is disabled (powered down) if the PLLEN field (
pllc
[15]) is cleared, which is the default after reset. The PLL is enabled (powered up)
if the PLLEN field (
pllc
[15]) is set.
§ The PLL is deselected if the PLLSEL field (
pllc
[14]) is cleared, which is the default after reset. The PLL is selected if the PLLSEL field
(
pllc
[14]) is set.
Typical Power Dissipation (mW)
Peripherals On
(powerc = 0x0000)
327
Peripherals Off
(powerc = 0x181F)
315
Normal Operation
PLL Disabled
and Deselected
§
CLK = CKI = 40 MHz
PLL Enabled
and Selected
§
pllc
= 0xEC0E
CKI = 10 MHz, CLK = 40 MHz
PLL Disabled
and Deselected
§
CLK = CKI = 40 MHz
PLL Enabled
and Selected
§
pllc
= 0xEC0E
CKI = 10 MHz, CLK = 40 MHz
340
328
Low-Power Standby Mode
(AWAIT (
alf
[15]) = 1)
51
39
64
52
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