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參數(shù)資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號處理器 |
| 文件頁數(shù)： | 41/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
41
Hardware Architecture
(continued)
Enhanced Serial I/O Unit (ESIO)
(continued)
Logical channels must be assigned in increasing output
channel start bit order and must not overlap. For exam-
ple, if channel 4 has a start bit of 48 and a sample
length of 4 bits (
OCSB2
[7:0] = 0x30;
OCSL0
[9:8] =
10), then channel 5 must have a start bit value greater
than or equal to 52 (48 + 4).
The ESIO reports an output frame error (EOFE) when
it is processing a valid frame and an output frame sync
is detected before the number of bits in the pro-
grammed frame length (OFRMSZ in
OCR
) have been
transmitted. If an EOFE interrupt occurs, the DSP pro-
gram should reset the output section by writing
OCR
with the ORESET bit set.
When driving output data in frame mode with EDO pro-
grammed as an open-drain device (EDOMD = 1 and
EDOEO = 1), the ESIO samples the EDO pin every
EOBC clock cycle. If the sampled value is not the
intended output value, the ESIO has collided with
another serial bus agent. When a bus collision is
detected, the ESIO asserts the output collision inter-
rupt (ECOL). The DSP program clears ECOL by writing
OCR
with either the ORESET field (bit 4) or the CRE-
SET field (bit 7) set.
Table 14 summarizes the ESIO interrupts. See
Table 7
on page 23
for information on request clearing latency
for these interrupts.
Table 14. ESIO Interrupts
Interrupt
Name
EIBF
Buffer
Description
Cleared By
Input
Full
Simple Mode
(IMODE = 1)
Asserted if a programmed number of input
bits (8 or 16 depending on ISIZE (
ICR
[7]))
have been captured following assertion of
the input frame sync.
Asserted after N nput frames (N= 2, 4, 8,
or 16, depending on IFIR[1:0] (
ICR
[1:0]))
have been received following input section
initialization
. If ICA (
ICR
[2]) remains set,
EIBF is reasserted after every subsequent
Nframes have been received.
Asserted if the input section is processing a
valid frame and an input frame sync is
detected before the number of bits speci-
fied by IFRMSZ[1:0] (
ICR
[11:10]) have
been sampled.
Asserted after the first bit (LSB) has been
output.
Asserted after the first bit (LSB) of the first
frame has been output following output
section initialization
§
. If OCA (
OCR
[2])
remains set, EOBE is reasserted at the
completion of every 2, 4, 8, or 16 frames
depending on OFIR[1:0] (
OCR
[1:0]).
Asserted if the output section is processing
a valid frame and an output frame sync is
detected before the number of bits in the
programmed frame length OFRMSZ[1:0]
(
OCR
[13:12]) have been transmitted.
Asserted if EDO is an open-drain output
(EDOMD (
OCR
[5]) = 1 and EDOEO
(
OCR
[6]) = 1) and the sampled EDO pin
value is not the intended output value.
Any of the following:
I
Device reset.
I
DSP program reads any of
IDMX
0—15
.
I
The DSP program sets the
IRESET field (
ICR
[4]).
Frame Mode
(IMODE = 0)
EIFE
Input
Frame
Error
Frame Mode
(IMODE = 0)
The DSP program sets the
IRESET field (
ICR
[4]).
EOBE
Output
Buffer
Empty
Simple Mode
(OMODE = 1)
Frame Mode
(OMODE = 0)
Any of the following:
I
Device reset.
I
DSP program writes
any of
OMX
0—15
.
I
The DSP program sets the
ORESET field (
OCR
[4]).
EOFE
Output
Frame
Error
Frame Mode
(OMODE = 0)
The DSP program sets the IRE-
SET field.
ECOL
Output
Collision
Frame Mode
(OMODE = 0)
The DSP program sets the
ORESET field (
OCR
[4]) or the
CRESET field (
OCR
[7]).
The DSP program initializes the input section by setting IRESET (
ICR
[4]) and ICA (
ICR
[2]).
This interrupt is disabled in simple mode.
§ The DSP program initializes the output section by setting ORESET (
OCR
[4]) and OCA (
OCR
[2]).
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