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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 40/173頁(yè) |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
40
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Enhanced Serial I/O Unit (ESIO)
(continued)
The clock OBCQ[15:0] is asserted in each frame for the
number of cycles that matches the programmed sam-
ple length for the corresponding logical channel. The
sample length is specified by one of the
OCSL
0—1
registers (see
Table 61 on page 103
).
Figure 15 is a timing diagram of the clock OBCQ3, the
bit clock for logical channel 3, assuming that the sam-
ple length is 2 bits (
OCSL0
[7:6] = 01) and the start bit
is 63 (
OCSB1
[15:8] = 0x3F). In Figure 15, D
0
is the
LSB and the initial output of the channel 3 parallel-to-
serial register (EDO3). The ESIO asserts the OCIX3
signal during the time slot for logical channel 3,
enabling EDO3 onto the EDO pin (see
Figure 14 on
page 38
). OBCQ3 is asserted for two cycles, shifting
the parallel-to-serial register contents by two bit posi-
tions, leaving D
2
on EDO3 for the next frame.
Figure 15. Serial Output Clocking Example
The ESIO asserts the EOBE output pin and the EOBE
interrupt on the falling edge of OBC after the detection
of the first OFS following output section initialization.
(See
Figure 13 on page 37
for an illustration of EOBE
timing and the discussion below for a description of
output section initialization.) EOBE is cleared when the
DSP program writes any of the
OMX
0—15
memory-
mapped registers. EOBE is also cleared on device
reset or if the DSP program resets the output section
by writing the
OCR
register with the ORESET field
(bit 4) set. The ESIO reasserts EOBE at the completion
of every 2, 4, 8, or 16 frames depending on the OFIR
field (bits [1:0]) of the
OCR
register (
Table 59 on
page 102
).
The programmer initializes the output section by simul-
taneously resetting it and enabling it, i.e., by writing
OCR
with the ORESET field set and the OCA field
(bit 2) set. The ORESET field clears itself automatically
every cycle of the internal clock (CLK). Therefore,
when
OCR
is read, the value of the ORESET field is
clear.
Prior to initializing the output section as described
above, the programmer must configure
OCVV
,
OCSB
0—7
, and
OCSL
0—1
. The write of
OCR
that
initializes the output section must also configure the
output section appropriately (OMODE, OFRMSZ, etc.).
Before changing any output channel attributes (e.g.,
OCVV
, OMODE), the programmer must first reset the
output section. Specifically, the programmer must write
OCR
with the ORESET field (bit 4) set and the OCA
field (bit 2) clear, change the attributes, and then
enable the output section by writing
OCR
with the OCA
field (bit 2) set.
In an environment with several different logical channel
sampling lengths, the EOBE generation rate should be
set to the highest parallel-to-serial transfer rate (see
Table 61 on page 103
). Each channel is serviced at its
programmed rate when a full word of output data has
been transmitted. For example, in a system with logical
channels of sample length 1, 2, and 8 bits, the highest
parallel-to-serial transfer rate is every 2 frames and
OFIR should be programmed to 0 (one EOBE every 2
frames). The channels with an 8-bit sample length
should be serviced every EOBE interrupt, the channels
with a 2-bit sample length should be serviced every
four EOBE interrupts, and the channels with a 1-bit
sample length should be serviced every eight EOBE
interrupts.
The OTMODE field (bit 11) of
OCR
can override the
parallel-to-serial transfer rate specified by
OCSL
0—1
.
When OTMODE is set to 1, data is transferred from
each
OMX
0—15
register to all 16 output shift regis-
ters simultaneously at the programmed OFIR fre-
quency.
The logical channels are enabled by programming the
16-bit
OCVV
register. Each bit in this register corre-
sponds to a logical channel, e.g., bit 5 of
OCVV
corre-
sponds to logical channel 5. When a bit in
OCVV
is set,
the ESIO multiplexes the output serial stream with data
from the corresponding channel. The bits in
OCVV
must be packed, i.e., channels must be allocated from
0 to 15 with no holes between valid channels. For
example, if
OCVV
contains 0x00FF, then logical chan-
nels 0—7 are enabled and multiplexed. A value of
0x08FF for
OCVV
is invalid because the channels are
not packed.
OBC
EDO3
D
0
D
1
OBCQ3
B
63
= D
0
B
64
= D
1
B
65
EDO
D
2
B
62
OCIX3
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