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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 28/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
28
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
External Memory Interface (EMI)
(continued)
Programmable Access Time
For each of the four external memory segments, the number of cycles to assert the enable can be selected in
mwait
(
Table 58 on page 101
). Within
mwait
, the IATIM[3:0] field specifies the number of cycles to assert the
enable for the IO segment, the YATIM[3:0] field specifies the number of cycles to assert the enable for the ERAMLO
and ERAMHI segments, and the XATIM[3:0] field specifies the number of cycles to assert the enable for the EROM
segment. On device reset, all access time values are initialized to 15 (
mwait
resets to 0x0FFF).
External memory accesses cause the core to incur wait-states.
Table 8 on page 28
defines the duration of an
access and the number of wait-states incurred as a function of the programmed access time (IATIM[3:0],
YATIM[3:0], or XATIM[3:0] abbreviated as A). For example, if YATIM[3:0] = 0xB (decimal 11), then the ERAMLO
and ERAMHI enables are asserted for 11 CLK cycles, any accesses to ERAMLO or ERAMHI require 12 CLK
cycles, and the number of wait-states incurred by the core is 12 for read operations and up to and including 12 for
write operations.
Wait-states for write operations can be transparent to the core if subsequent instructions do not access external
memory.
Table 8. Access Time and Wait-States
READY Pin Enables
For each of the four external memory segments,
mwait
(
Table 58 on page 101
) can be programmed to enable or
disable the READY pin. Setting the RDYEN2 bit enables READY for the IO segment, setting the RDYEN1 bit
enables READY for the ERAMLO and ERAMHI segments, and setting the RDYEN0 bit enables READY for the
EROM segment. On device reset, the RDYEN[2:0] bits are cleared, causing the DSP16210 to ignore the READY
pin by default.
Enable Delays
The leading edge of an enable can be delayed to avoid a situation in which two devices drive the data bus
simultaneously. If the leading edge of an enable is delayed, it is guaranteed to be asserted after the RWN signal is
asserted.
Setting DENB2 of
ioc
(
Table 54 on page 99
) delays the leading edge of the IO enable by approximately one half-
cycle of CLK. Similarly, setting DENB1 delays the leading edge of the ERAM, ERAMHI, and ERAMLO enables,
and setting DENB0 delays the leading edge of the EROM enable. On device reset, the DENB[2:0] bits are cleared,
causing no delay by default.
Memory Map Selection
The WEROM field (
ioc
bit 4) selects either YMAP0 or YMAP1 (see
Figure 6 on page 26
). If WEROM is set,
YMAP1 is selected and all ERAMLO accesses are mapped to EROM. This allows the EROM segment, which is
normally read-only, to be written. For example, a program could download code or coefficients into the EROM seg-
ment for later use. If WEROM is set, the DENB1 field (
ioc
bit 1) and the RDYEN1 and YATIM[3:0] fields (
mwait
bits 13 and 7—4) control Y-side accesses to EROM.
Number of CLK Cycles
the Enable Pin Is Asserted
IATIM[3:0], YATIM[3:0], or XATIM[3:0]
(abbreviated as ATIM)
1—15
Duration of
Access
ATIM + 1
Wait-States Incurred
Read
ATIM + 1
Write
Quantity
up to and including ATIM + 1
Range
2—16
2—16
0—16
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