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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 18/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
18
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
DSP16000 Core Architectural Overview
(continued)
Table 2. DSP16000 Core Block Diagram Legend
(continued)
Reset
The DSP16210 has two negative-assertion external
reset input pins: RSTB and TRST. RSTB is used to
reset the DSP16210. The primary function of TRST is
to reset the JTAG controller.
Reset After Powerup or Power Interruption
At initial powerup or if power is interrupted,
a reset is
required and both TRST and RSTB must be asserted
(low) simultaneously for at least seven CKI cycles (see
Reset Circuit on page 142
for details). The TRST pin
must be asserted even if the JTAG controller is not
used by the application. Failure to properly reset the
device on powerup or after a power interruption can
lead to a loss of communication with the DSP16210
pins.
RSTB Pin Reset
Reset initializes the state of user registers, synchro-
nizes the internal clocks, and initiates code execution.
The device is properly reset by asserting RSTB (low)
for at least seven CKI cycles. After RSTB is deas-
serted, there is a delay of several CKI cycles before the
device begins executing instructions (see
Reset Syn-
chronization on page 143
for details). The DSP16210
samples the state of the EXM pin when RSTB is deas-
serted to determine whether it boots from IROM at
location 0x20000 (EXM = 0) or from EROM at location
0x80000 (EXM = 1). See
Reset States on page 113
for
the values of the user registers after reset.
Table 3 on page 19
defines the states of the output and
bidirectional pins both during and after reset. It does
not include the TDO output pin, because its state is not
affected by RSTB but by the JTAG controller.
vbase
vsw
x
XAAU
XAB
XDB
y
YAAU
YAB
YDB
Vector Base Offset Register
Viterbi Support Word—associated with the traceback encoder
Multiplier Input Register
X-Memory Space Address Arithmetic Unit
X-Memory Space Address Bus
X-Memory Space Data Bus
Multiplier Input Register
Y-Memory Space Address Arithmetic Unit
Y-Memory Space Address Bus
Y-Memory Space Data Bus
Symbol
Name
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