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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 19/173頁(yè) |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
19
Reset
(continued)
RSTB Pin Reset
(continued)
Table 3. State of Device Output and Bidirectional Pins During and After Reset
JTAG Controller Reset
The recommended method of resetting the JTAG con-
troller is to assert RSTB and TRST simultaneously. An
alternative method is to clock TCK through at least five
cycles with TMS held high. Both methods ensure that
the user has control of the device pins. JTAG controller
reset does not initialize user registers, synchronize
internal clocks, or initiate code execution unless RSTB
is also asserted.
Reset of the JTAG controller places it in the test logic
reset (TLR) state. While in the TLR state, the
DSP16210 3-states all bidirectional pins, clears all
boundary-scan cells for unidirectional outputs, and
deasserts (high) all external memory interface enable
signals (EROM, ERAM, ERAMHI, ERAMLO, and IO).
This prevents logic contention.
Type
Pin
State of Pin During Reset
(RSTB = 0)
3-state
State of Pin After Reset
(RSTB 0
→
1)
logic low
Output
AB[15:0], EIBF, PIBF,
IBF, IACK
EOBE, POBE, OBE
DO
EDO
RWN, EROM,
ERAMHI, ERAMLO,
ERAM, IO
3-state
3-state
3-state
logic high
3-state
3-state
logic high
INT0 = 0
(deasserted)
INT0 = 1
(asserted)
INT0 = 0
(deasserted)
INT0 = 1
(asserted)
logic high
3-state
CKO
internal clock
(CLK = CKI)
3-state
During and after reset, the internal clock is selected as the CKI input pin and the CKO output pin is selected as the internal clock.
The
ioc
register (
Table 54 on page 99
) is cleared after reset, including its EBIO field that controls the multiplexing of the VEC0/IOBIT7,
VEC1/IOBIT6, VEC2/IOBIT5, and VEC3/IOBIT4 pins. Therefore, after reset, these pins are configured as the VEC[3:0] outputs, which are ini-
tialized as logic high during reset.
internal clock
(CLK = CKI)
Bidirectional
(Input/Output)
VEC[3:0]/IOBIT[7:4]
IOBIT[3:0], TRAP,
OLD, OCK, ILD, ICK
DB[15:0], PB[15:0]
3-state
3-state
logic high
configured as input
3-state
3-state
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