
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
11
Hardware Architecture
(continued)
DSP16210 Architectural Overview
(continued)
Table 1. DSP16210 Block Diagram Legend
Symbol
BIO
Bit I/O Unit
cbit
BIO Control Register
CLK
Internal Clock Signal
DPRAM
Dual-port Random-Access Memory
EAB
EMI Address Bus
EDB
EMI Data Bus
ESIO
Enhanced Serial I/O Unit
HDS
Hardware Development System Unit
ICR
ESIO Input Control Register
ICSB
0—7
ESIO Input Channel Start Bit Registers
ICSL
0—1
ESIO Input Channel Sample Length Registers
ICVV
ESIO Input Channel Valid Vector Register
IDMX
0—15
ESIO Input Demultiplexer Registers
ID
JTAG Device Identification Register
IDB
Internal Data Bus
ioc
I/O Configuration Register
IORAM0
Internal I/O RAM 0: Shared with MIOU0
IORAM1
Internal I/O RAM 1: Shared with MIOU1
IROM
Internal Boot Read-Only Memory
jiob
JTAG Test Register
JTAG
JTAG Test Port
MIOU0
Modular I/O Unit 0: Controls PHIF16
mcmd0
MIOU0 Command Register
miwp0
MIOU0 IORAM0 Input Write Pointer
morp0
MIOU0 IORAM0 Output Read Pointer
MIOU1
Modular I/O Unit 1: Controls SSIO
mcmd1
MIOU1 Command Register
miwp1
MIOU1 IORAM1 Input Write Pointer
morp1
MIOU1 IORAM1 Output Read Pointer
mwait
EMI Configuration Register
OCR
ESIO Output Control Register
OCSB
0—7
ESIO Output Channel Start Bit Registers
OCSL
0—1
ESIO Output Channel Sample Length Registers
OCVV
ESIO Output Channel Valid Vector Register
OMX
0—15
ESIO Output Multiplexer Registers
PDX
(in)
PHIF16 Input Register; Readable by MIOU0
PDX
(out)
PHIF16 Output Register; Writable by MIOU0
PHIF16
16-bit Parallel Host Interface
PHIFC
PHIF16 Control Register: Programmed Through MIOU0
PLL
Phase-Lock Loop
pllc
Phase-Lock Loop Control Register
Description